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Hardware support for real-time embedded multiprocessor system-on-a-chip memory management

Mohamed Shalan, Vincent J. Mooney
2002 Proceedings of the tenth international symposium on Hardware/software codesign - CODES '02  
(SoCDMMU) for allocation of the global on-chip memory, which we refer to as Level Two memory management (Level One is the operating system management of memory allocated to a particular on-chip Processing  ...  In this paper, we show how to modify an existing Real-Time Operating System (RTOS) to support the new proposed SoCDMMU.  ...  Architecture such as this will be suitable for embedded real-time applications.  ... 
doi:10.1145/774789.774806 dblp:conf/codes/ShalanM02 fatcat:4clecm7zbjb4bmo4zrvrqxe2oq

Hardware support for real-time embedded multiprocessor system-on-a-chip memory management

Mohamed Shalan, Vincent J. Mooney
2002 Proceedings of the tenth international symposium on Hardware/software codesign - CODES '02  
(SoCDMMU) for allocation of the global on-chip memory, which we refer to as Level Two memory management (Level One is the operating system management of memory allocated to a particular on-chip Processing  ...  In this paper, we show how to modify an existing Real-Time Operating System (RTOS) to support the new proposed SoCDMMU.  ...  Architecture such as this will be suitable for embedded real-time applications.  ... 
doi:10.1145/774801.774806 fatcat:vw54odtjhfgwhps6uupcbghvgu

Hardware support for real-time embedded multiprocessor system-on-a-chip memory management

M. Shalan, V.J. Mooney
Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627)  
(SoCDMMU) for allocation of the global on-chip memory, which we refer to as Level Two memory management (Level One is the operating system management of memory allocated to a particular on-chip Processing  ...  In this paper, we show how to modify an existing Real-Time Operating System (RTOS) to support the new proposed SoCDMMU.  ...  Architecture such as this will be suitable for embedded real-time applications.  ... 
doi:10.1109/codes.2002.1003605 fatcat:owqodmg47nat7cuaowmqhhkesi

The future of multiprocessor systems-on-chips

Wayne Wolf
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
A multiprocessor system-onchip includes embedded processors, digital logic, and mixedsignal circuits combined into a heterogeneous multiprocessor.  ...  This mix of technologies creates a major challenge for MPSoC design teams. We will look at some existing MPSoC designs and then describe some hardware and software challenges for MPSoC designers.  ...  Acknowledgments Thanks to Ahmed Jerraya, Alain Mellan, Faraydon Karim, Santanu Dutta, Pierre Paulin, and Phil Koopman for fruitful discussions about multiprocessor systems-on-chips.  ... 
doi:10.1145/996566.996753 dblp:conf/dac/Wolf04 fatcat:welw7ysflfgbhff6cvizv7mkee

Guest Editors' Introduction: Multiprocessor Systems-on-Chips

A. Jerraya, H. Tenhunen, W. Wolf
2005 Computer  
Researchers have been studying memory systems for symmetric multiprocessors for many years, and MPSoCs often use heterogeneous memory systems to improve real-time performance and power consumption.  ...  But irregular memory structures are often necessary in MPSoCs. One reason that designers resort to specialized memory is to support real-time performance.  ... 
doi:10.1109/mc.2005.231 fatcat:ddegaas42zbkdlkgylycvyslqi

Adaptive Data Placement in an Embedded Multiprocessor Thread Library

P. Stanley-Marbell, K. Lahiri, A. Raghunathan
2006 Proceedings of the Design Automation & Test in Europe Conference  
Embedded multiprocessors pose new challenges in the design and implementation of embedded software.  ...  In addition, for systems that implement applications consisting of multiple concurrent threads of computation, the optimized management of interthread communication is crucial for realizing high-performance  ...  One challenge in the use of such embedded multiprocessors is the dearth of appropriate programming interfaces for effectively exploiting hardware-level concurrency.  ... 
doi:10.1109/date.2006.244065 dblp:conf/date/Stanley-MarbellLR06 fatcat:qgsjbrfrwzby7h272beokdoboe

Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors

Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2006 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications.  ...  The data allocation on the physically distributed shared memory space is dynamically managed by an on-chip Hardware Memory Management Unit.  ...  For this purpose, a distributed shared memory architecture has been proposed, that is suitable for low-power on-chip multiprocessors and supported by an on-chip hardware MMU.  ... 
doi:10.1109/icsamos.2006.300821 dblp:conf/samos/MonchieroPSV06 fatcat:cu6537637na4vgk3bfthdjxuoe

An Approach to Advance Real-Time Os Services with Soft-Error

Swapan Debbarma, Kunal Chakma
2011 International Journal of Computer and Electrical Engineering  
Index Terms-Real-Time OS; soft-error; embedded conFig.urable operating system (eCOS) I.  ...  Real-Time Operating System (RTOS) users desire predictable response time at an affordable cost, due to this demand Hardware/Software Real-Time Operating Systems (HW/SW-RTOS) appeared.  ...  The approach also provides higher performance and better predictability for real-time applications running on an MPSoC. • SoCDMMU The System-on-a-Chip Dynamic Memory Management Unit (SoCDMMU) is a hardware  ... 
doi:10.7763/ijcee.2011.v3.377 fatcat:mozu34vyijabpgdz7dbgn3c7te

Embedded computer architectures in the MPSoC age

Wayne Wolf
2005 Proceedings of the 2005 workshop on Computer architecture education held in conjunction with the 32nd International Symposium on Computer Architecture - WCAE '05  
Multiprocessor Systems-on-Chips Multiprocessor systems-on-chips (MPSoCs) [Jer04] are, first of all, systems-on-chips. They implement complete applications on a single chip.  ...  Embedded computing provides students different take on computer system design because of the requirements imposed on these systems: • Embedded computing systems generally require real-time performance.  ... 
doi:10.1145/1275604.1275607 dblp:conf/wcae/Wolf05 fatcat:ihdtjoimcbgbhpm2p4cek4tgsa

Exploration of distributed shared memory architectures for NoC-based multiprocessors

Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2007 Journal of systems architecture  
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications.  ...  The data allocation on the physically distributed shared memory space is dynamically managed by an on-chip Hardware Memory Management Unit.  ...  For this purpose, a distributed shared memory architecture has been proposed, that is suitable for low-power on-chip multiprocessors and supported by an on-chip hardware MMU.  ... 
doi:10.1016/j.sysarc.2007.01.008 fatcat:6jjvd42x2vetdmai3ftipxlg5e

TrustGeM: Dynamic trusted environment generation for chip-multiprocessors

Luis Angel D. Bathen, Nikil D. Dutt
2011 2011 IEEE International Symposium on Hardware-Oriented Security and Trust  
; security; chip-multiprocessors; policy; embedded raids-on-chip; isolation; scheduling I.  ...  In this paper, we introduce TrustGeM: a dynamic trusted environment generation engine for chip-multiprocessors.  ...  The main contributions or this paper are: • SeReVral: Secure, reliable, and dynamic memory virtualization support for CMPs • SeReVral-aware policy generation • SeReVral-aware real-time on-chip application  ... 
doi:10.1109/hst.2011.5954994 dblp:conf/host/BathenD11 fatcat:sex2lg4bljeefcgjyvy5ppo77a

FPGA Based Embedded Multiprocessor Architecture

Sumedh. S. Jadhav, C.N. Bhoyar
2013 International Journal of Electronics and Electical Engineering  
The design methodology is expected to allow scalable embedded multiprocessors for system expansion.  ...  Multiprocessor is a typical subject within the Computer architecture field of scope. A new methodology based on practical sessions with real devices and design is proposed.  ...  ACKNOWLEDGEMENTS Authors wish to remark the great task carried out by the Xilinx and Modelsim user guide; and the authors wish to thanks Prof.C.N.Bhoyar for his contribution in the design process.  ... 
doi:10.47893/ijeee.2013.1042 fatcat:5xogwpkczzcjloex6h23pkt7eq

STORM a simulation tool for real-time multiprocessor scheduling evaluation

R Urunuela, A Déplanche, Y Trinquet
2010 2010 IEEE 15th Conference on Emerging Technologies & Factory Automation (ETFA 2010)  
The increasing complexity of the hardware multiprocessor architectures as well as of the real-time applications they support makes very difficult even impossible to apply the theoretical real-time multiprocessor  ...  Thus, so as to be able to evaluate and compare real-time multiprocessor scheduling strategies on their schedulability performance as well as energy efficiency, we have preferred a simulation approach and  ...  For a given problem i.e. a software application that has to run on a (multiprocessor) hardware architecture, this simulator is able to play its execution over a specified time interval while taking into  ... 
doi:10.1109/etfa.2010.5641179 dblp:conf/etfa/UrunuelaDT10 fatcat:6clefohfo5do7dd5xe6ynsh2vm

Creating HW/SW co-designed MPSoPC's from high level programming models

Eugene Cartwright, Sen Ma, David Andrews, Miaoqing Huang
2011 2011 International Conference on High Performance Computing & Simulation  
FPGA densities have continued to follow Moore's law and can now support a complete multiprocessor system on programmable chip.  ...  We use OpenCL as our specification framework and show how key API's are extracted and used to automatically create a distributed shared memory multiprocessor system on chip architecture for Xilinx FPGA's  ...  CONCLUSION FPGA densities have continued to follow Moore's law and can now support a complete multiprocessor system on programmable chip.  ... 
doi:10.1109/hpcsim.2011.5999874 dblp:conf/ieeehpcs/CartwrightMAH11 fatcat:5z3445b6xvbmjlz7tc5lziwiv4

Towards a Java multiprocessor

Christof Pitter, Martin Schoeberl
2007 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems - JTRES '07  
This paper describes the first steps towards a Java multiprocessor system on a single chip for embedded systems.  ...  The chip multiprocessing (CMP) system consists of a homogeneous set of processing elements and a shared memory. Each processor core is based on the Java Optimized Processor (JOP).  ...  Acknowledgement The TPCM-project received support from the Austrian FIT-IT SoC initiative, funded by the Austrian Ministry for Traffic, Innovation and Technology (BMVIT) and managed by the Austrian Research  ... 
doi:10.1145/1288940.1288962 dblp:conf/jtres/PitterS07 fatcat:kymjieugtfg4va4l375ek256ue
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