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Exploring the limits of early register release

Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oğuz Ergin
2009 ACM Transactions on Architecture and Code Optimization (TACO)  
Register pressure in modern superscalar processors can be reduced by releasing registers early and by copying their contents to cheap back-up storage.  ...  Using simple compiler analysis and microarchitecture changes, we achieve 70% of the potential register file occupancy reduction. By adding more hardware support, we can increase this to 94%.  ...  In addition to this, we added support for checkpoints and banking to the register file and the ability to release registers early, as described in Sections 6.1, 6.2, and 6.3.  ... 
doi:10.1145/1582710.1582714 fatcat:tjlrpgtys5bo7c7tw2j27ouvqa

Compiler directed early register release

T.M. Jones, M.F.R. O'Boyle, J. Abella, A. Gonzalez, O. Ergin
2005 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)  
This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early.  ...  This reduces the occupancy of our banked register file, allowing banks to be turned off for power savings. Our scheme is faster, simpler and requires less hardware than recently proposed techniques.  ...  Acknowledgements This work has been partially supported by The Spanish Ministry of Education and Science under grants TIC2001-0995-C02-01, TIN2004-03072, FEDER funds and Intel Corporation.  ... 
doi:10.1109/pact.2005.14 dblp:conf/IEEEpact/JonesOAGE05 fatcat:wcy4bz3ribeznojxb47at26ela

Microarchitectural Support for Speculative Register Renaming

Jesus Alastruey, Teresa Monreal, Victor Vinals, Mateo Valero
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
To support the location of register operands being either in PRF or XRF, we use virtual registers. We consider omission and release policies directed by hardware prediction.  ...  We call speculative renaming to the speculative omission of physical register allocation along with the speculative early release of physical registers.  ...  Acknowledgments This work was supported in part by Diputación General de Aragón grant "Grupo Consolidado de Investigación" (BOA 20/04/2005), Spanish Ministry of Education and Science grant TIN2004-07739  ... 
doi:10.1109/ipdps.2007.370237 dblp:conf/ipps/AlastrueyMVV07 fatcat:hggapxfprbc25aiahtgsjvn6du

Turn antiquated peek and poke interfaces in embedded module to modern web APIs

IJIRT Journal
2020 Figshare  
During the early stage of development and debugging embedded board designs, developers may need to read (peek) values from hardware and write (poke) values into its registers or memory address before developing  ...  In Embedded system, peek and poke are the fundamental command sets available in command line interface to read or write memory address or hardware registers.  ...  This hardware register level debugging support is not only critical during the development, it could also be utilized as a backdoor method of debugging when system is released in the field.  ... 
doi:10.6084/m9.figshare.12530384 fatcat:wylpztp5nbfcvmswxjwmmx2dne

Leveraging Register Windows to Reduce Physical Registers to the Bare Minimum

Eduardo Quinones, Joan-Manuel Parcerisa, Antonio Gonzalez
2010 IEEE transactions on computers  
Index Terms-Register Windows, Physical Register File, Early Register Release  ...  In this paper, we propose a software/hardware early register release technique that leverage register windows to drastically reduce the register requirements, and hence reduce the register file cost.  ...  Early Register Release Techniques without Compiler Support Context Release takes full advantatge of call conventions.  ... 
doi:10.1109/tc.2010.85 fatcat:yyvh6tl4kjhzppdmh7xrtdlnxm

Checkpointed early load retirement

N. Kirman, M. Kirman, M. Chaudhuri, J.F. Martinez
2005 11th International Symposium on High-Performance Computer Architecture  
Our evaluation shows that a Clear implementation with support for four checkpoints yields an average speedup of 1.12 for both eleven integer and eight floating-point applications (1.27 and 1.19 for five  ...  To attack this problem, we propose checkpointed early load retirement, a mechanism that combines register checkpointing and back-end-i.e., at retirement-load-value prediction.  ...  ACKNOWLEDGMENTS We thank the anonymous reviewers for useful feedback. This work was supported in part by NSF grant CCF-0429922 and gifts from Intel.  ... 
doi:10.1109/hpca.2005.9 dblp:conf/hpca/KirmanKCM05 fatcat:jupfyzt6rvdsblvccvle5hqudu

A group-commit mechanism for ROB-based processors implementing the X86 ISA

F. Afram, Hui Zeng, K. Ghose
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
Further, the destination registers of instructions from a group that do not hold the most recent updates to architectural registers, can be released before the group containing these instructions is committed  ...  We introduce an alternative instruction commitment mechanism for a Reorder Buffer (ROB)based out-of-order processor that commits a group of consecutive instructions atomically to support a larger instruction  ...  Early Register Releases Our group-commit mechanism supports early register releases: registers not targeted by the last writers in a group can be released as soon as the last consumer of each such register  ... 
doi:10.1109/hpca.2013.6522306 dblp:conf/hpca/AframZG13 fatcat:mpa4nplnuzfmpkqpjejspmffwq

Early Register Release for Out-of-Order Processors with RegisterWindows

Eduardo Quinones, Joan-Manuel Parcerisa, Antonio Gonzalez
2007 Parallel Architecture and Compilation Techniques (PACT), Proceedings of the International Conference on  
In this paper we propose two early register release techniques that leverages register windows to drastically reduce the register requirements, and hence reduce the register file cost.  ...  Such register requirements are normally increased for out-of-order execution because it requires registers for the in-flight instructions, in addition to the architectural ones.  ...  Acknowledgements This work is supported by the Spanish Ministry of Education and Science and FEDER funds of the EU under contracts TIN 2004-03072, and TIN 2004-07739-C02-01, and Intel Corporation.  ... 
doi:10.1109/pact.2007.4336214 fatcat:kbjtxenamjdutarn5asyqtqv4m

Compiler-assisted, selective out-of-order commit

Nam Duong, Alex V. Veidenbaum
2013 IEEE computer architecture letters  
Micro-architectural support for the new commit mode is made on top of the standard, ROB-based processor and includes out-of-order instruction commit with register and load queue entry release.  ...  Initial results for a 4-wide processor show that, on average, 52% instructions are committed out of order resulting in 10% to 26% speedups over in-order commit, with minimal hardware overhead.  ...  For this reason early release of physical registers was not allowed in [2] . The block information is used to solve these and to allow a selective OOO register release.  ... 
doi:10.1109/l-ca.2012.8 fatcat:5tvsuunrufaqllfypriv7b346q

Kilo-Instruction Processors: Overcoming the Memory Wall

A. Cristal, O.J. Santana, F. Cazorla, M. Galluzzi, T. Ramirez, M. Pericas, M. Valero
2005 IEEE Micro  
This approach is much less effective for the long L2 cache misses, however. For example, along the top of Figure 1 is a sequence of instructions in program order. Following a  ...  Doing so means designing key hardware structures so that the processor can satisfy the high resource requirements without significantly decreasing processor efficiency or increasing energy consumption.  ...  Acknowledgments This work has been supported by the Ministry of Education of Spain under contract TIN-2004-07739-C02-01, the HiPEAC European Network of Excellence, and the Barcelona Supercomputing Center  ... 
doi:10.1109/mm.2005.53 fatcat:3d7vmnewlzg65jfw2dltm4ta5y

Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit

Mehdi Alipour, Trevor E. Carlson, David Black-Schaffer, Stefanos Kaxiras
2018 Journal of Signal Processing Systems  
) until they are released in program order.  ...  The disadvantage of in-order commit (IOC) is that it ties up resources (such as reorder buffer [ROB] entries, loadstore queue [LSQ] entries, and physical registers) for a much longer time than is necessary  ...  Speculative Release of Hardware Structures A number of implementations require register and processor state checkpointing support to speculatively retire or release hardware structures [1, 11, 12, 17,  ... 
doi:10.1007/s11265-018-1369-4 fatcat:7sfqsebcqrgxfibgxqmaoozkci

ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory

Jaewoong Chung, Luke Yen, Stephan Diestelhorst, Martin Pohlack, Michael Hohmuth, David Christie, Dan Grossman
2010 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture  
Programmers can use speculative regions to build flexible multi-word atomic primitives with no additional software support by relying on the minimum guarantee of available ASF hardware resources for lock-free  ...  Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory.  ...  They agreed that composability with nesting is important for transactional programming but argued that this may have to be supported by software at least for early ASF implementations.  ... 
doi:10.1109/micro.2010.40 dblp:conf/micro/ChungYDPHCG10 fatcat:ujplokdepvdbjcsqefva3nkvwa

Hardware description languages

1988 Integration  
Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques.  ...  Hardware description languages are special purpose programming languages.  ...  VHDL • DOD required common HDL to support designs from different vendors. • DOD contract awarded in 1983. • Strong Ada influence. • Public released 1985.  ... 
doi:10.1016/0167-9260(88)90027-2 fatcat:6irsfgvwjbf6lcoewuryghv3va

Late allocation and early release of physical registers

T. Monreal, V. Vinals, J. Gonzalez, A. Gonzalez, M. Valero
2004 IEEE transactions on computers  
Detailed cycle-level simulations show either a significant speedup for a given register file size or a reduction in the register file size for a given performance level, especially for floating-point codes  ...  Index Terms-Register renaming, out-of-order processors, register file optimization, physical register allocation and releasing, precise exceptions. ae  ...  The authors would like to thank the Associate Editor for his useful suggestions and the referees for their insightful comments.  ... 
doi:10.1109/tc.2004.79 fatcat:qtnt7jkurrbcfbqcocvj7khcsq

Reconfigurable, XML-driven, OO framework for real-time control and monitoring of embedded Radar Signal Processor

Carel J. Combrink, Chris J. Venter, Seshan Govender, Mohammed A. Alshareef
2011 2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)  
Design and scope changes are also minimized through the use of a dynamic scheme for addressing, controlling and monitoring hardware.  ...  The Unified Process was used for the development of the CMF.  ...  The CMF performs version management which provides support for new versions to be added easily while maintaining support for older versions.  ... 
doi:10.1109/siecpc.2011.5876938 fatcat:sbuh2najlrfdbpjixfgovqmyqa
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