Filters








542 Hits in 4.4 sec

Hardware implementation of a FPGA-based universal link for LVDS communications

Luis Sanchez, Giancarlo Patino, Victor Murray, James Lyke
2015 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS)  
We present the first hardware implementation for a FPGA-based universal link for the transmission of different low-voltage differential signaling (LVDS) connections through a single LVDS connection between  ...  We propose a solution for one of the difficulties of LVDS standard due to the amount of wires needed for a duplex connection, significantly reducing the amount of wires required for a large network.  ...  Fig. 1 . 1 Universal link for N different communications channels (c 0 , c 1 , · · · , c N −1 ) using LVDS. (a) N communication systems working individually. (b) Same system using an universal link.  ... 
doi:10.1109/lascas.2015.7250480 dblp:conf/lascas/SanchezPML15 fatcat:g55y4i2edra5xnabclbuq7t6gi

Flexible FPGA-based controller architecture for five-fingered dexterous robot hand with effective impedance control

Z. P. Chen, N. Y. Lii, K. Wu, H. Liu, Z. X. Xue, M. H. Jin, Y. W. Liu, S. W. Fan, T. Lan
2009 2009 IEEE International Conference on Robotics and Biomimetics (ROBIO)  
The key feature of the hardware system is a dual-processor architecture based controller, one of which is used for data communication control and the other for joint and object level control.  ...  , are all implemented on a single FPGA chip.  ...  Benedikt Pleintinger of the German Aerospace Center (DLR) for their technical support.  ... 
doi:10.1109/robio.2009.5420731 dblp:conf/robio/ChenLWLXJLFL09 fatcat:er5qvabobzb3dnfsfu4we4wesu

Hardware Design and Protocol Specification for the Control and Communication Within a Mechatronic System [chapter]

André Luiz de Freitas Francisco, Achim Rettberg, Andreas Hennig
2004 IFIP International Federation for Information Processing  
Key words: This paper describes a communication system for the test track that will be used to develop the components of a new train concept, the RailCab.  ...  The demand for flexible hardware architecture and optimized communication channels motivated this project.  ...  The architecture of the four servo stations is shown in figure 3 . For these stations, each SSI board has connections for up to 8 servos and a LVDS link to a router ( fig. 3) .  ... 
doi:10.1007/1-4020-8149-9_12 fatcat:fp7kzsoq5vao3dnotz4hja635m

FPGA based Multichannel Bit Error Rate Tester for Spacecraft Data Acquisition System

Manoj Kumar A, R V Nadagouda, R Jegan
2014 International Journal of Reconfigurable and Embedded Systems (IJRES)  
In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix II (EP2S130F1508C5N) FPGA.  ...  Bit Error Rate (BER) is a principle measure of data transmission link performance. BER tester (BERT) consists of a Pattern Generator and an Analyzer that can be set to the same pattern.  ...  ACKNOWLEDGEMENTS The authors would like to thank Spacecraft Checkout Group, ISRO Satellite Centre, Bangalore, India, for providing lab facilities and supporting the project.  ... 
doi:10.11591/ijres.v3.i2.pp76-84 fatcat:qnlbvlln4fcs3dhhaxupemvksq

MDDI Protocol Packet Generation Method of Mobile System

Jong-Moon Kim, Chang-Su Kim, Hoe-Kyung Jung
2014 International Journal of Multimedia and Ubiquitous Engineering  
In this paper, the method of creating data in software, which was notpresent in the previous FPGA is proposed for design of data transmitter using the MDDI interface method.  ...  The previously proposed method to create MDDI protocol packet was implemented in FPGA.  ...  In addition, it confirmed normal working to the FIFO works of FPGA and the LVDS output under the hardware function.  ... 
doi:10.14257/ijmue.2014.9.1.14 fatcat:tn35dballndhzl4ifoljx5pra4

Development of a digital readout board for the ATLAS Tile Calorimeter upgrade demonstrator

S Muschter, H Aakerstedt, K Anderson, C Bohm, M Oreglia, F Tang
2014 Journal of Instrumentation  
We report on the hybrid system's FPGA based communication module that is responsible for receiving and unpacking commands using a 4.8 Gbps downlink and driving a high bandwidth data uplink.  ...  The report includes key points like multi-gigabit transmission, clock distribution, programming and operation of the hardware.  ...  Here one should use state-of-the-art optical links to achieve the required bandwidth and radiation tolerant FPGAs for flexibility and redundance.  ... 
doi:10.1088/1748-0221/9/01/c01001 fatcat:bhk7zd3fyfgmhmlb5ttls7b4zi

The Gigabit Link Interface Board (GLIB) ecosystem

P Vichoudis, J Andresen, S Baron, M Barros Marin, V Bobillier, J Chramowitz, S Haas, M Hansen, M Joos, L Lobato Pardavila, P Petit, A Prosser (+1 others)
2013 Journal of Instrumentation  
The Gigabit Link Interface Board (GLIB) project is an FPGA-based platform for users of high-speed optical links in high energy physics experiments.  ...  This article focuses on the development of the auxiliary components that together with the GLIB AMC offer a complete solution for beam/irradiation tests of detector modules and evaluation of optical links  ...  Hazen of Boston University for providing the FPGA firmware for the TTC decoding, originally developed for the AMC13.  ... 
doi:10.1088/1748-0221/8/03/c03012 fatcat:xco2rkj2bff7diak3xjtgzfn7e

MPI as an abstraction for software-hardware interaction for HPRCs

Manuel Saldana, Arun Patel, Christopher Madill, Daniel Nunes, Danyao Wang, Henry Styles, Andrew Putnam, Ralph Wittig, Paul Chow
2008 2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications  
need for a system-level Hardware/Software co-design development flow.  ...  This paper presents the evolution and current work on TMD-MPI, which started as an MPI-based programming model for Multiprocessor Systems-on-Chip implemented in FPGAs, and has now evolved to include multiple  ...  ACKNOWLEDGMENT We acknowledge the CMC/SOCRN, NSERC and Xilinx for the hardware, tools and funding provided for this project.  ... 
doi:10.1109/hprcta.2008.4745682 fatcat:k7zocyygpneafa4k3slwt2hc3a

Design of a 128‐channel transceiver hardware for medical ultrasound imaging systems

Jayaraj Kidav, Perumal M. Pillai, Deepak V, Sreejeesh S. G
2021 IET Circuits, Devices & Systems  
In this work, the design and development of a 128-channel transceiver hardware for medical ultrasound imaging systems and research is presented.  ...  Besides, compared to the commercial open ultrasound research scanners, the flexibility to interface FPGA-based signal processing module helps to investigate the performance of hardware realisation of various  ...  To validate similar kinds of algorithm implementations on FPGA, a multichannel ultrasound front-end hardware with the capability to stream a higher number of channel data to FPGA-based processing hardware  ... 
doi:10.1049/cds2.12087 fatcat:axy5nierbjapbi4ewengtbbpgy

Live demonstration: A scalable 32-channel neural recording and real-time FPGA based spike sorting system

Ian Williams, Song Luan, Andrew Jackson, Timothy G. Constandinou
2015 2015 IEEE Biomedical Circuits and Systems Conference (BioCAS)  
The hardware consists of: an Intan RHD2132 neural amplifier; a low power Igloo ® nano FPGA; and an FX3 USB 3.0 controller.  ...  Graphical User Interfaces for controlling the system, displaying real-time data, and template generation with a modified form of WaveClus are demonstrated.  ...  Fig. 2 . 2 (a) System hardware overview, (b) Data flow through the system. a PC -the functions of each are described below. Standard HDMI and USB3 cables are used to link the boards.  ... 
doi:10.1109/biocas.2015.7348330 dblp:conf/biocas/WilliamsLJC15 fatcat:2qesllam6rf2jesq3s2nnxomci

A Modular Data Acquisition System using the 10 GSa/s PSEC4 Waveform Recording Chip [article]

M. Bogdan, E. Oberla, H.J. Frisch, M. Wetstein
2016 arXiv   pre-print
The system architecture incorporates two levels of hardware with FPGA-embedded system control and in-line data processing.  ...  The front-end unit is a 30-channel circuit board that holds five PSEC4 ASICs, a clock jitter cleaner, and a control FPGA. The analog bandwidth of the front-end signal path is 1.5 GHz.  ...  ACKNOWLEDGMENTS We thank Mary Heintz, Jean-Francois Genat, Hervé Grabas, Kurtis Nishimura, Harold Sanders, Fukun Tang, and Gary Varner for their essential contributions.  ... 
arXiv:1607.02395v1 fatcat:nmf3ovvlnnajlcxzq6dgxxpaqe

Prototype performance studies of a Full Mesh ATCA-based General Purpose Data Processing Board [article]

Yasuyuki Okumura, Jamieson Olsen, Tiehui Ted Liu, Hang Yin
2014 arXiv   pre-print
Communication between nodes requires high bandwidth, low latency, and flexible real time data sharing, for which a full mesh backplane is a natural solution.  ...  High luminosity conditions at the LHC pose many unique challenges for potential silicon based track trigger systems.  ...  Fig. 4 . 4 The FPGAs are interfaced to (a) local bus connecting two FPGAs on the board, (b) ATCA full mesh backplane for use of point-to-point links and (c) pluggable transceivers on RTM.  ... 
arXiv:1403.4331v1 fatcat:2tnfdo3k3ngzxfiiffcrsuujcu

Portable data acquisition system based on FPGA and USB

Cao Qiang, Zhang Jun, Xiong Xing
2013 International Journal of Intelligent Engineering and Systems  
We also introduced the concrete realization of the design of clock part, LVDS converter module and USB control module. The programming language used verilog hardware description language.  ...  In this paper, we designed a high-speed, high-precision, portable data acquisition and processing system in Altera Corporation cyclone II FPGA platform, and achieved the communication between the system  ...  Acknowledgments This work is supported by the National Science Foundation of China (grants 61071204) and the Development Foundation of Tianjin University of Technology and Education (grants KJY11-3).  ... 
doi:10.22266/ijies2013.0630.03 fatcat:ec4342kryvcmroz7ul2eqqi5kq

Design and implementation of a low-cost fault-tolerant on-board computer for micro-satellite

Shiqiang Tian, Zuobiao Yin, Jian Yan, Xuming Liu
2012 7th International Conference on Communications and Networking in China  
The purpose of this paper is to present a solution for developing a low-cost, low power consumption and reliable OBC system for micro-satellites.  ...  Besides, considering the harsh space environment, a set of fault tolerant strategies are introduced to improve the reliability of the OBC.  ...  Four LVDS links are implemented through FPGA2 and LVDS drivers and act as the high-speed data transmission channels. B.  ... 
doi:10.1109/chinacom.2012.6417462 dblp:conf/chinacom/TianYYL12 fatcat:2qadesy3wnfi5ih4b4n7clfrke

Backplane Serial Signaling And Protocol For Telecom Systems

Ali Poureslami, Hossein Borhanifar, Seyed Ali Alavian
2010 Zenodo  
For combination high reliability and low cost protocol property, we applied high level data link control (HDLC) protocol with low voltage differential signaling (LVDS) bus for card to card communicated  ...  In this paper, we implement a modern serial backplane platform for telecommunication inter-rack systems.  ...  ACKNOWLEDGMENT The authors would like to thank Iran Telecom Research Center (ITRC) organization for full project supporting.  ... 
doi:10.5281/zenodo.1072329 fatcat:qzaix2lp65gf5hgv632g53qmhy
« Previous Showing results 1 — 15 out of 542 results