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Turbo codes for Tb/s communications: code design and hardware architecture

Ronald Garzon-Bohorquez, Charbel Abdel Nour, Stefan Weithoffer, Catherine Douillard, Norbert Wehn
2019 Zenodo  
Catherine Douillard (from IMT Atlantique) gave a presentation entitled "Turbo codes for Tb/s communications: code design and hardware architecture" at the Oberpfaffenhofen Workshop on High Throughput Coding  ...  What can make the LTE turbo code suitable for B5G communication systems? ■ How to lower the error floor?  ...  ■ How to lower the error floor?  ... 
doi:10.5281/zenodo.3484780 fatcat:m2fxu5fbobfrvhnpohmudygqfu

Turbo codes for Tb/s communications: code design and hardware architecture

Ronald Garzon-Bohorquez, Charbel Abdel Nour, Stefan Weithoffer, Catherine Douillard, Norbert Wehn
2019 Zenodo  
A presentation of Turbo codes for Tb/s communications: code design and hardware architecture, which was given at the Workshop on High Throughput coding, in Munich, Germany  ...  What can make the LTE turbo code suitable for B5G communication systems? ■ How to lower the error floor?  ...  ■ How to lower the error floor?  ... 
doi:10.5281/zenodo.3565341 fatcat:qaknxfpifngilnuysm3263p7qa

A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE

Ji-Hoon Kim, In-Cheol Park
2009 2009 IEEE Custom Integrated Circuits Conference  
We propose a new hardware architecture that can share hardware resources for the two standards.  ...  This paper describes the energy-efficient implementation of a high performance parallel radix-4 turbo decoder, which is designed to support multiple fourth-generation (4G) wireless communication standards  ...  This Section explains in detail the proposed chip architecture developed to share hardware resources for Mobile WiMAX and 3GPP-LTE. A.  ... 
doi:10.1109/cicc.2009.5280790 dblp:conf/cicc/KimP09 fatcat:va2xi4uwtfedldxg43boebqkpa

Low complexity state metric compression technique in turbo decoder

Qingqing Yang, Xiaofang Zhou, Gerald E. Sobelman, Xinxin Li
2013 IEICE Electronics Express  
The framework of the compression circuit is given. BER performances for several turbo decoders are simulated.  ...  For four state turbo codes, 30.1% logic gates and 75% memory bits are required.  ...  Fig. 4 plots the BER curve for turbo code in 3GPP-LTE with information length of 1024. Fig. 5 shows the WIMAX case with 1920 information bits.  ... 
doi:10.1587/elex.10.20130485 fatcat:p6fz6ni4wbhvpc4pmxxfvocyee

A High-Throughput FPGA Architecture for Joint Source and Channel Decoding

Matthew F. Brejza, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo
2017 IEEE Access  
We demonstrate the application of these improvements to both the LTE turbo code and the UEC code.  ...  The recently proposed Unary Error Correction (UEC) code facilitates the Joint Source and Channel Coding (JSCC) of video information at transmission throughputs that approach the capacity of the wireless  ...  Figure 7 depicts a fully parallel decoder for the LTE turbo code of Section II-A2.  ... 
doi:10.1109/access.2016.2633441 fatcat:nxq3wwg625buxi77a2m2gcstcm

High speed low complexity radix-16 Max-Log-MAP SISO decoder

Oscar Sanchez, Christophe Jegoy, Michel Jezequel, Yannick Saouter
2012 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)  
Thus, a penalty lower than 0.05dB is observed for a 8 state binary turbo code with respect to a traditional radix-2 turbo decoder for 6 decoding iterations.  ...  Based on the elimination of parallel paths in the radix-16 trellis diagram, architectural solutions to reduce the hardware complexity of the different blocks of a SISO decoder are detailed.  ...  We have observed a penalty around 0.2dB, for code rates R = 1/2 and 1/3, at FER of 10 −6 , with an error floor that remains high compared to the error floor of a radix-2 SISO architecture.  ... 
doi:10.1109/icecs.2012.6463718 dblp:conf/icecsys/SanchezJJS12 fatcat:2a3jsqspqvbcbe2n4pruer43lu

A Parallelized Implementation of Turbo Decoding Based on Network on Chip Multi - core Processor

Chaolong ZHANG, Institute of Microelectronics , Chinese Academy of Sciences, Beijing 10029, China, Zhekun HU, Jie Chen, The 709th Research In stitute of China Shipbuilding Industry Corporation, Wuhan 430009, China, Institute of Microelectronics , Chinese Academy of Sciences, Beijing 10029, China
2014 Journal of Engineering Science and Technology Review  
Several aspects of turbo decoder are investigated in software radio approach rather than hardware.  ...  The NOC is well balanced between the hardware and software design with a high degree of programmability and re-configurability.  ...  Acknowledgements This work was financially supported by the National Natural Science Foundation of China (No. 61201265, No. 61221004 and No. 61376027). ______________________________ References  ... 
doi:10.25103/jestr.071.09 fatcat:whr5ppbtizdl7fizmhpr6ebhou

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

Shuai Shao, Peter Hailes, Tsang-Yi Wang, Jwo-Yuh Wu, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo
2019 IEEE Communications Surveys and Tutorials  
The powerful turbo code was selected to provide channel coding for Mobile Broad Band (MBB) data in the 3G UMTS and 4G LTE cellular systems.  ...  Channel coding may be viewed as the bestinformed and most potent component of cellular communication systems, which is used for correcting the transmission errors inflicted by noise, interference and fading  ...  More specifically, the URLLC channel code must not exhibit an error floor above a Block Error Rate (BLER) of 10 −5 [25] .  ... 
doi:10.1109/comst.2019.2893851 fatcat:rv2p4a4ol5c2dneveopxsxwqqq

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

An Li, Peter Hailes, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo
2016 IEEE Access  
In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction.  ...  These are respectively 13.2 times and 11.1 times superior to those of the state-ofthe-art FPGA implementation of the Log-BCJR Long-Term Evolution (LTE) turbo decoder, when decoding frames of the same frame  ...  The floor truncation is applied to the product after the decimal point ( ). Fig. 11 : 11 The datapath for the termination unit of the proposed fixedpoint FPTD for the case of the LTE turbo code.  ... 
doi:10.1109/access.2016.2599408 fatcat:gvso2qxw2vdyriwx5vznbt4wva

Multimode Flex-Interleaver Core for Baseband Processor Platform

Rizwan Asghar, Dake Liu
2010 Journal of Computer Systems, Networks, and Communications  
The presented hardware enables the mapping of vital types of interleavers including multiple block interleavers and convolutional interleaver onto a single architecture.  ...  By exploiting the hardware reuse methodology the silicon cost is reduced, and it consumes 0.126 mm2area in total in 65 nm CMOS process for a fully reconfigurable architecture.  ...  The channel coding block in HAPA+ including WCDMA uses turbo coding [37] for forward error correction. 3GPP standard [4] proposes the algorithm for block interleaving in turbo encoding/decoding as  ... 
doi:10.1155/2010/793807 fatcat:bxjsyr6vvndhfdbvmnwjla64ku

On the performance of LDPC and turbo decoder architectures with unreliable memories

Joao Andrade, Aida Vosoughi, Guohui Wang, Georgios Karakonstantis, Andreas Burg, Gabriel Falcao, Vitor Silva, Joseph R. Cavallaro
2014 2014 48th Asilomar Conference on Signals, Systems and Computers  
Our study investigates the inherent error resilience of such codes to potential memory faults affecting the decoding process.  ...  In this paper, we investigate the impact of faulty memory bit-cells on the performance of LDPC and Turbo channel decoders based on realistic memory failure models.  ...  I, for the DVB-S2 LDPC and 3GPP LTE/LTE-Advanced Turbo rate 1/3 codes, with block length N as defined in Tbl. II.  ... 
doi:10.1109/acssc.2014.7094504 dblp:conf/acssc/AndradeVWKBFSC14 fatcat:oacpnurpcnakbclarckm27ai3u

VLSI Implementation of Fully Parallel LTE Turbo Decoders

An Li, Luping Xiang, Taihai Chen, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo
2016 IEEE Access  
INDEX TERMS Fully-parallel turbo decoder, VLSI design, LTE turbo code. NOMENCLATURE  ...  Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable iterative forward error correction.  ...  of the proposed fixed-point FPTD for the case of the LTE turbo code.  ... 
doi:10.1109/access.2016.2515719 fatcat:7ua5vo3xlrdanla77cbnlaj4ou

High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver

Cheng-Chi Wong, Hsie-Chia Chang
2011 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
This paper presents a high-efficiency parallel architecture for a turbo decoder using a quadratic permutation polynomial (QPP) interleaver.  ...  Due to the initialization calculation and pipeline delays in every half-iteration, the functional units in turbo decoders will be idle for several cycles.  ...  ACKNOWLEDGMENT The authors thank the Chip Implementation Center, UMC, and NCTU Si2 Lab for their assistance.  ... 
doi:10.1109/tcsi.2010.2097690 fatcat:ehhuewjlx5dsdlfr22e63wreeu

Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System

Cheng-Chi Wong, Hsie-Chia Chang
2010 IEEE Transactions on Circuits and Systems - II - Express Briefs  
This brief presents a parallel architecture for the turbo decoder using the quadratic permutation polynomial interleaver.  ...  Index Terms-3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE), quadratic permutation polynomial (QPP) interleaver, turbo decoder.  ...  ACKNOWLEDGMENT The authors would like to thank UMC, NCTU Si2 Lab, NCTU-MTK Research Center, and CIC for their assistance.  ... 
doi:10.1109/tcsii.2010.2048481 fatcat:b7yi4zysmzfmhfap4nl54u4hmy

Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets

Gummidipudi Krishnaian, Nur Engin, Sergei Sawitzki
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
The aim of this paper is to investigate the feasibility of a programmable channel decoder that can be dynamically reconfigured for decoding turbo and convolutionally encoded streams from various wireless  ...  The resulting decoder architecture supports hardware resource sharing and reconfiguration between different standards and decoders and is more efficient in terms of silicon area than independent implementation  ...  The lower BER performance of SOVA and high complexity of MAP make using same algorithm for both turbo and Viterbi an unfavorable option.  ... 
doi:10.1109/date.2007.364524 fatcat:rvux2w3e6raqvi2c3fvz72vkga
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