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Hardware Synthesis of A Parallel JPEG Decoder from Its Functional Specification [chapter]

John Hawkins, Ali E. Abdallah
IFIP International Federation for Information Processing  
Starting with a clear, intuitively correct specification of the problem, in a functional language such as Haskell, we apply a set of formal transformation laws to refine it into a behavioural definition  ...  We apply this technique to a non-trivial, real world problem -a JPEG decompression algorithm, and achieve a truly scalable, parallel hardware implementation.  ...  We have illustrated this with the development of a JPEG decoding algorithm, starting from a high level and intuitive specification in Haskell, and using this to derive a parallel Handel-C program that  ... 
doi:10.1007/1-4020-8149-9_20 dblp:conf/ifip10-3/HawkinsA04 fatcat:lzuwmar2t5fuxpy4jegc36qeda

A unified hardware/software co-synthesis solution for signal processing systems

Endri Bezati, Herve Yviquel, Michael Raulet, Marco Mattavelli
2011 Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)  
As a proof of concept a JPEG codec was written purely in RVC-CAL to test the co-synthesis tools and then an analysis of the generated hardware and software results are given.  ...  This paper presents a methodology to specify from a highlevel data-flow description an application for both hardware and software synthesis.  ...  and hardware code synthesis from the same specification.  ... 
doi:10.1109/dasip.2011.6136877 dblp:conf/dasip/BezatiYRM11 fatcat:b6fdgzvxxjfjfdoaxi5ss5daim

Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs

Ghislain Roquier, Endri Bezati, Marco Mattavelli
2012 Journal of Electrical and Computer Engineering  
This paper presents a design flow for the hardware and software synthesis of heterogeneous systems allowing to automatically generate hardware and software components as well as appropriate interfaces,  ...  The new generation of multicore processors and reconfigurable hardware platforms provides a dramatic increase of the available parallelism and processing capabilities.  ...  To this end, additional to the JPEG encoder, we developed a JPEG decoder in RVC-CAL for creating a baseline profile JPEG Journal of Electrical and Computer Engineering codec.  ... 
doi:10.1155/2012/484962 fatcat:yylyrvov45go5gdsn2gx4rwj4a


Christian Haubelt, Thomas Schlichter, Joachim Keinert, Mike Meredith
2008 Proceedings of the 45th annual conference on Design automation - DAC '08  
Starting from a behavioral SystemC model, hardware accelerators can be generated automatically using Forte Cynthesizer and can be added to the design space.  ...  As a result, SystemCoDesigner presents optimized hardware/software solutions to the designer who can select any of them for rapid prototyping on an FPGA basis.  ...  Starting from a Ptolemy application model, it provides a seamless codesign flow from functional simulation to system synthesis. Moreover, PeaCE supports the generation of an FPGA prototype.  ... 
doi:10.1145/1391469.1391616 dblp:conf/dac/HaubeltSKM08 fatcat:p7cn7wnmkfchrma2477dvmoski

Fault-Tolerant in Embedded Systems (MPSoC): Performance Estimation and Dynamic Migration Task

Kamel Smiri, Habib Smei, Nourhen Fourati, Abderrazak Jemai
2017 Advances in Science, Technology and Engineering Systems  
An application can be modeled as a set of cooperative tasks. A task can be implemented in software or in hardware depending on its complexity and the involved cost.  ...  We exploited an example of multimedia application (MJPEG decoder) to find optimal Fault tolerance systems. Our aim in this paper is to exploit the classic technique of fault tolerance.  ...  The MOTION JPEG decoder reads a stream of JPEG images from an input peripheral: a traffic generator named TG and writes pixels on an output peripheral: a digital-to-analogue converter named RAMDAC.  ... 
doi:10.25046/aj0203150 fatcat:ow6tiyfjo5dghfscyemtpibkdy

A Fast Performance Estimation Framework for System-Level Design Space Exploration

Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2012 IPSJ Transactions on System LSI Design Methodology  
A case study on design space exploration of a JPEG decoder system demonstrates the effectiveness of our framework.  ...  In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including  ...  Processes in the JPEG decoder can run in parallel in a pipelined manner.  ... 
doi:10.2197/ipsjtsldm.5.44 fatcat:f2jkth4eh5cavaohfm3qeocgti

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

Endri Bezati, Richard Thavot, Ghislain Roquier, Marco Mattavelli
2013 Journal of Real-Time Image Processing  
Experimental results on the implementation of a JPEG codec and a MPEG 4 SP decoder on heterogeneous platforms demonstrate the flexibility and capabilities of this design approach.  ...  This study describes a dataflow-based design methodology aiming at a unified co-design and co-synthesis of heterogeneous systems.  ...  Additionally to the JPEG encoder, we designed a JPEG decoder for creating a motion JPEG codec, represented in Fig. 8 .  ... 
doi:10.1007/s11554-013-0326-5 fatcat:lnullnukzfg4haq2dnobeqib2e

A processor core synthesis system in IP-based SoC design

Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed caiculation algorithm. We can USE!  ...  In our approach, after system-level HW/SW partitioning, we use IPS for hardware parts, but synthesize a new processor core instead of reusing a processor core IP.  ...  It has a detapath, some registers, an instruction pipeline to hold the hardware-IP-instructions from the processor core and an instruction decode logic to decode the hardware-IPinstructions.  ... 
doi:10.1145/1120725.1120851 dblp:conf/aspdac/TomonoKUMTYO05 fatcat:66mpnba2l5h7phoy2stxgg7kr4

Multiprocessor mapping of process networks

E. A. de Kock
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
We apply the method to implement a JPEG decoding process network in software on a set of MIPS processors.  ...  We use process networks as re-usable and architecture-independent functional specifications.  ...  Subsequently, system designers can transform the functions for a specific architecture taking into account its costs and constraints, such that the functions can be implemented efficiently in hardware  ... 
doi:10.1145/581199.581216 fatcat:3bcpllwn6zgqne6riwv2tv3lhq

Multiprocessor mapping of process networks

E. A. de Kock
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
We apply the method to implement a JPEG decoding process network in software on a set of MIPS processors.  ...  We use process networks as re-usable and architecture-independent functional specifications.  ...  Subsequently, system designers can transform the functions for a specific architecture taking into account its costs and constraints, such that the functions can be implemented efficiently in hardware  ... 
doi:10.1145/581214.581216 fatcat:zgbid3vrzjdsjkmvly2ektycme

A parallel/serial trade-off methodology for look-up table based decoders

Claus Schneider
1997 Proceedings of the 34th annual conference on Design automation conference - DAC '97  
Hardware cost (area) and feasibility (timing) are determined by synthesis of RTL models.  ...  A methodology for architecture exploration of look-up table based decoders is presented.  ...  A Parallel/Serial Trade-Off Methodology for Look-Up Parallel/Serial Trade-Off Methodology For the parallel/serial trade-off of a variable length decoder, top-down information from the system level as  ... 
doi:10.1145/266021.266213 dblp:conf/dac/Schneider97 fatcat:7wg25y7cyzazjewhqurrjvl2ma

JPEG Image Compression using the Discrete Cosine Transform: An Overview, Applications, and Hardware Implementation [article]

Ahmad Shawahna, Md. Enamul Haque, Alaaeldin Amin
2019 arXiv   pre-print
In this paper, we present the architecture and implementation of JPEG compression using VHDL (VHSIC Hardware Description Language) and compare the performance with some contemporary implementation.  ...  There are both lossy and lossless image compression format available and JPEG is one of the popular lossy compression among them.  ...  ACKNOWLEDGMENT The authors would like to thank the department of Computer Engineering, King Fahd University of Petroleum and Minerals, Saudi Arabia.  ... 
arXiv:1912.10789v1 fatcat:gt56hzzi3rbgtm53kklvxwqnfe

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

Affaq Qamar, Fahad Bin Muslim, Javed Iqbal, Luciano Lavagno
2017 Microprocessors and microsystems  
This research aims to integrate low power techniques, specifically Power Shut-Off (PSO), within a model based hardware flow and to derive an automated Low Power-High Level Synthesis (LP-HLS) methodology  ...  All the information that is needed to implement low power techniques is automatically derived from the systemlevel design using a set of pragmas and a directives file.  ...  simulation of a JPEG-IDCT decoder.  ... 
doi:10.1016/j.micpro.2017.02.002 fatcat:vvlqqmmtnzeorm6odadyfidb4e

Multi-processor programming in the embedded system curriculum

Andreas Hansson, Benny Akesson, Jef van Meerbergen
2009 ACM SIGBED Review  
In the course, groups of four students are faced with the problem of putting an embedded JPEG decoder on the market within one semester.  ...  Teaching embedded system design is challenging, as the subject covers a wide range of aspects, and also involves skills that students do not learn from a text book.  ...  A more scalable solution exploits functional parallelism by mapping the decoding functions to different cores.  ... 
doi:10.1145/1534480.1534489 fatcat:otwvf3kkdve7pp52flepfkux2m

Adaptively Lossy Image Compression for Onboard Processing

Justin Goodwill, David Wilson, Sebastian Sabogal, Alan D. George, Christopher Wilson
2020 2020 IEEE Aerospace Conference  
The first algorithm, CNN-JPEG, employs a hybrid approach adapted from literature combining convolutional neural networks (CNNs) and JPEG; however, we modify and tune the training scheme for satellite imagery  ...  We achieve a less than 1% drop in average PSNR and SSIM while reducing the combined file size by 29.6% compared to JPEG using a static quality factor (QF) of 90.  ...  [16] uses a similar codec structure of a nonlinear analysis transform, quantizer, and synthesis transform.  ... 
doi:10.1109/aero47225.2020.9172536 fatcat:ou6b74ywjnckfjxwgicb7nlx4i
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