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Baseband Hardware Designs in Modernised GNSS Receivers [chapter]

Nagaraj C., Andrew G.
2012 Global Navigation Satellite Systems: Signal, Theory and Applications  
Carrier mixer (N 1 ) The carrier mixer basically multiplies the input signal with the local carrier bits.  ...  The carrier mixer output results in N 1 -bit values. 35 Baseband Hardware Designs in Modernised GNSS Receivers which then demands a separate address generator.  ... 
doi:10.5772/32774 fatcat:gkjsteer7ngtxmlpydce3uwb34

Implementation of PSK Digital Demodulator with Variable Rate Based on FPGA

Xiquan Xia
2015 Open Automation and Control Systems Journal  
The proposed design has its hardware test in the Xilinx Virtex-5 FPGA platform.  ...  QPSK modulation digital system with variable rate, a novel implementation method based on field programmable gate array (FPGA) is proposed, which can support 4.88Kbps to 2Mbps and even higher continuous bit  ...  In order to verify the design proposed in this article through hardware, the mixer must work under the sampling frequency of ADC in the structure.  ... 
doi:10.2174/1874444301507011280 fatcat:x2kcawur7bfsfchm4bgkshanji

Receiver control for the Submillimeter Array [article]

T.R. Hunter, R.W. Wilson, R. Kimberk, P.S. Leiker, R.D. Christensen
2005 arXiv   pre-print
Efficient operation of a submillimeter interferometer requires remote (preferably automated) control of mechanically tuned local oscillators, phase-lock loops, mixers, optics, calibration vanes and cryostats  ...  Since various receiver hardware components require linear or rotary motion, each microcontroller also implements a position servo via a one-millisecond interrupt service routine which drives a DC-motor  ...  12-bit ADC to monitor the mixer bias, mixer current, magnetic field, receiver total power and other voltages.  ... 
arXiv:astro-ph/0509761v1 fatcat:ecanurx2dberlkpitoewatxv4a

A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters

Shalabh Goyal, Abhijit Chatterjee, Michael Purtell
2007 Journal of electronic testing  
The test methodology was verified in simulations as well as in hardware with specification estimation error of less than 5%.  ...  Hardware Set-Up The proposed test methodology was validated on a 14-bit 40 Msps A/D converter using the Catalyst tester. A set of 55 devices was taken.  ...  Hardware Validation of the Proposed Approach The proposed approach was validated on a 14-bit 40 Msps A/D converter manufactured by National Semiconductor.  ... 
doi:10.1007/s10836-006-9523-5 fatcat:gsa33veswje2rgjrasfcorlmvu

Customizable sponge-based authenticated encryption using 16-bit S-boxes

Matthew Kelly, Alan Kaminsky, Michael Kurdziel, Marcin Lukowiak, Stanislaw Radziszowski
2015 MILCOM 2015 - 2015 IEEE Military Communications Conference  
In this paper we introduce a novel authenticated encryption algorithm based on the duplex construction that is targeted for hardware implementation.  ...  step uses 16 × 16 AES-like S-boxes which are novel because they are the largest bijective S-boxes to be used by an encryption scheme in the literature and are still efficiently implementable in both hardware  ...  represents a 16-bit word the largest S-boxes used in the literature are the 8 × 8 bijective S-boxes used by the AES [13] Fig. 5 . 5 Hardware implementation of the forward mixer function Bitwise PermutationStep  ... 
doi:10.1109/milcom.2015.7357416 dblp:conf/milcom/KellyKKLR15 fatcat:7kqpgbqzjjgfbkcwckirsnpdvm

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Chester Sungchung Park, Sunwoo Kim, Jooho Wang, Sungkyung Park
2021 Electronics  
From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models.  ...  A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in  ...  Next, the bit-accurate model is constructed, which also closely resembles the hardware behavior and furthermore applies quantization that occurs in digital hardware.  ... 
doi:10.3390/electronics10030231 fatcat:ox7onpm2e5exvnctxcc2jr6dfi

FPGA Implementation of Fuzzy Interpreted Petri Net

Zbigniew Hajduk, Jolanta Wojtowicz
2020 IEEE Access  
However it must be pointed out that the update time of the FIPN hardware implementation may be affected by the number of implementation's bits (the Q parameter).  ...  SIMULATIONS AND IMPLEMENTATION RESULTS The FIPN from Fig. 9 has been described in Verilog Hardware Description Language using methods presented in Section III for the number of bits amounting to 12 (  ... 
doi:10.1109/access.2020.2983276 fatcat:hq3gpllxvrfkte5mpf4gefjaua

Design & Analysis of an X-Band QPSK Modulator using Direct Carrier Modulation Technique

Maria Siddiqua
2006 2006 IEEE International Multitopic Conference  
The circuit has been designed at 8.3 GHz X Band for 150Mbps bit rate.  ...  The selection of a Double Balanced Mixer, being the main component of the design, is a critical issue. Specifications of mixer such as Conversion loss, Interport isolation etc are discussed.  ...  These problems can be removed using passive double balanced mixers.  ... 
doi:10.1109/inmic.2006.358145 fatcat:vl3lqgbhbbdqtbsfyg6suvkiye

Universal Hardware and Software System of Signal Converting for Integrated Sensor Devices Implementation

Hryhorii Barylo, Oksana Boyko, Igor Helzhynskyy, Roman Holyaka, Tetyana Marusenkova, Mariia Ivakh
2021 2021 IEEE 16th International Conference on the Experience of Designing and Application of CAD Systems (CADSM)  
of 16 mV/bit.  ...  Up mixer is continuous-time balance mixer, which performs the function of signals switching multiplier and Down mixer is discrete-time mixer, that performs the function of sample-and-hold of the signal  ... 
doi:10.1109/cadsm52681.2021.9385254 fatcat:ntvfp6ncrvb3na2m6jgppikebu

Page 608 of SMPTE Motion Imaging Journal Vol. 102, Issue 7 [page]

1993 SMPTE Motion Imaging Journal  
The Transform hardware is com- posed of the following components: VME interface, source buffer, desti- nation buffer, transform engine, inter- polation pipeline, mixer, and sequencer.  ...  The output of the graphics genera- tor is a 32-bit digital stream of pixels with 8 bits for each of the red, green, blue, and key components.  ... 

A two-stage angle-rotation architecture and its error analysis for efficient digital mixer implementation

Dengwei Fu, A.N. Willson
2006 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
An efficient angle-rotation architecture, suitable for use in a digital mixer, is presented.  ...  This error analysis is shown to lead to a straightforward means of designing an efficient two-stage angle-rotation unit for a digital mixer, given input/output bitwidths and performance specifications.  ...  For each bit increase, we get one more bit of precision at the output. Therefore, we can design the processor to have minimal hardware for a given output precision requirement.  ... 
doi:10.1109/tcsi.2005.859056 fatcat:4hwfqa23mfa4pfumwkodedmjta

IoT enabled communication device with mixer less low complex QPSK based transmitter architecture for low frequency applications

M. P. R. Sai Kiran, P. Rajalakshmi, B. Jagadish
2014 2014 International Symposium on Wireless Personal Multimedia Communications (WPMC)  
Integrating mixers is a challenging task, especially in mixed signal design. IoT communication devices require low design complexity as we expect millions of devices connected.  ...  In this paper we propose a mixer less low complex QPSK based transmitter architecture targeting low frequency applications which reduced the complexity in transmitter design.  ...  The number of bits transmitted in each of the phases are same.  ... 
doi:10.1109/wpmc.2014.7014837 dblp:conf/wpmc/KiranRJ14 fatcat:bhapwyxq4rhxloxlpivywoaqjy

Real-time data reorganizer for the d0 central fiber tracker trigger system at fermilab

S.M. Rapisarda, N.G. Wilcer, J.T. Olsen
2003 IEEE Transactions on Nuclear Science  
The Mixer System processes 311 Gigabits per second of data with an input to output delay of 200 nanoseconds.  ...  A custom digital data Mixer system has been designed to reorganize, in real time, the data produced by the Fermilab D0 Scintillating Fiber Detector.  ...  Tomoto for their invaluable help in the assembly, debugging, and commissioning of the Mixer system.  ... 
doi:10.1109/tns.2003.815163 fatcat:zgs5h246lfd7lappvqt2wdn7ny

A programmable multi-GNSS baseband receiver

Vinh T Tran, Nagaraj C Shivaramaiah, Oliver Diessel, Andrew G Dempster
2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS)  
Hardware time multiplexing is more effective technique. It, however, requires an efficient memory hierachy and an efficient code generator design.  ...  The resource consumption of a Rtap PPC that consists of N 1 -bit Carrier Mixer, N ref -bit Local Reference signal, N 2 -bit Local Reference Mixer and N acc -bit Accumulators, however, is still high as:  ...  r = (2 * N 1 + N ref ) R λ (2*N1+Nref ) R-bit registers + 2R α * N 1 + N ref m 2R (N1+Nref )-bit LUT Mixer + N acc 2 Nacc-bit Adder + 2 * log 2 R i=1 R 2 i i + N 2 − 1 2 2 Tree Network Adder + 2 * R K  ... 
doi:10.1109/iscas.2015.7168849 dblp:conf/iscas/TranSDD15 fatcat:nz2wrvb3srbjlp7mm63h4uxwwq

A quantum alternating operator ansatz with hard and soft constraints for lattice protein folding [article]

Mark Fingerhuth, Tomáš Babej, Christopher Ing
2018 arXiv   pre-print
Gate-based universal quantum computers form a rapidly evolving field of quantum computing hardware technology.  ...  This stands in contrast with current quantum annealing hardware, where the mixer Hamiltonian is fixed by the chosen hardware implementation and cannot be defined by the user [15] .  ...  Yet, the XY and XZ mixers fail at converting these strings into feasible solutions whilst the X mixer can achieve this by simply flipping the respective bits.  ... 
arXiv:1810.13411v1 fatcat:sob6jczanvh4fkt34jp3epyarm
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