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Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems

Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich, Michael Wagner
2020 International Conference on High Performance Embedded Architectures and Compilers  
for on-line use, and the advantage of the proposed task migration approach over mapping reconfiguration as the state-of-the-art real-time adaptation approach for many-core systems.  ...  For a variety of applications and many-core platforms, we experimentally demonstrate the feasibility of hard real-time task migrations, the lightness of the proposed timing analysis and feasibility check  ...  for hard real-time applications.  ... 
doi:10.4230/ dblp:conf/hipeac/PourmohseniSWT20 fatcat:6744kxoa7fhy7bwwbbpwpunrnq

Virtual Architectures for partial runtime reconfigurable systems. Application to Network on Chip based SoC emulation

Y.E. Krasteva, E. de la Torre, T. Riesgo
2008 2008 34th Annual Conference of IEEE Industrial Electronics  
Such pRTR system is used as a core for a Network on Chip based SoC emulation. The main advantage of the emulation framework is that it permits fast emulation and design space exploration.  ...  The paper presents a method for designing Virtual Architectures (VAs) for partial runtime reconfigurable systems (pRTRs). The presented method permits to create flexible pRTRs.  ...  ACKNOWLEDGMENT The authors wish to express their gratitude to the Departamento de Fundamentos da Computacao, Pontificia Universidade Catolica do Rio Grande do Sul, specially to Ney Calazans, for providing  ... 
doi:10.1109/iecon.2008.4758347 fatcat:pljvonyew5ed7fd7pqvuxugfbu

Maintaining real-time application timing similarity for defect-tolerant NoC-based many-core systems

Zheng Li, Frank Lockom, Shangping Ren
2014 ACM Transactions on Embedded Computing Systems  
Many-core Network-on-Chip (NoC) processors are emerging in broad application areas, including those with timing requirements, such as real-time and multimedia applications.  ...  many-core NoC.  ...  Network On Chip (NoC) Many-Core Processor Model Our many-core NoC model is based on a 2D mesh topology with homogeneous cores under XY routing.  ... 
doi:10.1145/2544375.2544384 fatcat:4ftnbge54nd45pboiklyqgufki

A greedy approach to tolerate defect cores for multimedia applications

Ke Yue, Soumia Ghalim, Zheng Li, Frank Lockom, Shangping Ren, Lei Zhang, Xiaowei Li
2011 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia  
Based on this metric, we develop a greedy algorithm to reconfigure a defecttolerant manycore platform and form a unified application specific virtual topology on which the timing variations caused by the  ...  As a result, a fine-tuned application based on timing parameters given by one topology may not meet the expected timing behavior under the new one.  ...  Ma et. al [6] conducted system-level exploration of mesh-based NoC architectures for multimedia applications.  ... 
doi:10.1109/estimedia.2011.6088517 dblp:conf/estimedia/YueGLLRZL11 fatcat:zz55uetylzax7pxcygrdj4fh6y

Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC

Ke Yue, Frank Lockom, Zheng Li, Soumia Ghalim, Shangping Ren, Lei Zhang, Xiaowei Li
2012 17th Asia and South Pacific Design Automation Conference  
For a given application's task graph and a task to core mapping strategy, the traffic pattern on the NoC is known a priori.  ...  Based on this metric, a Hungarian method based algorithm is developed to reconfigure a defect-tolerant manycore platform and form a unified application specific virtual core topology of which the timing  ...  We are all aware that for hard real-time applications, minimizing task-to-task communication time change may not guarantee stringent timing properties required by these applications.  ... 
doi:10.1109/aspdac.2012.6165003 dblp:conf/aspdac/YueLLGRZL12 fatcat:a5orhxker5aibb52bjpr4ofpjy

Towards a Modular RISC-V based Many-Core Architecture for FPGA Accelerators

Ahmed Kamaleldin, Salma Hesham, Diana Gohringer
2020 IEEE Access  
The motivation behind this work is to introduce a modular cluster-based many-core architecture for FPGA accelerators that is re-usable and flexible tailored to implement different many-core taxonomies  ...  Multi-/Many-core architectures are emerging as scalable, high-performance and energy-efficient computing platforms suitable for a variety of application domains from edge to cloud computing.  ...  RVNoC [13] framework is a design time configurable RISC-V NoC-based MPSoC to integrate many RISC-V cores using a reconfigurable NoC architecture to allow large system scalability in term of computing  ... 
doi:10.1109/access.2020.3015706 fatcat:zwknt4ke3nhvbgjdsh4ppoi4xu

Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective

Behnaz Pourmohseni, Michael Glaß, Jörg Henkel, Heba Khdr, Martin Rapp, Valentina Richthammer, Tobias Schwarzer, Fedor Smirnov, Jan Spieck, Jürgen Teich, Andreas Weichslgartner, Stefan Wildermann
2020 Journal of Low Power Electronics and Applications  
Hybrid Application Mapping (HAM) is an emerging class of design methodologies for many-core systems which address these challenges via an incremental (per-application) mapping scheme: The mapping process  ...  We introduce the basics of HAM and elaborate on the way it addresses the major challenges of application mapping in many-core systems.  ...  The hybrid (design-time/run-time) mapping scheme in HAM offers a unique opportunity for supporting hard real-time applications in dynamic embedded systems.  ... 
doi:10.3390/jlpea10040038 fatcat:3pde6c5gmvcchifub3xnxpcm7u

Hardware and software infrastructure to implement many-core systems in modern FPGAs

Felipe T. Bortolon, Fernando G. Moraes
2017 Proceedings of the 30th Symposium on Integrated Circuits and Systems Design Chip on the Sands - SBCCI '17  
While FP-GAs provide a rich reconfigurable hardware fabric, only one or two embedded hard-core processors are available to execute complex software applications.  ...  Therefore, modern FPGAs offer the possibility to merge the benefits of many-core systems with the reconfigurability of FPGAs.  ...  multi/many-core systems.  ... 
doi:10.1145/3109984.3109997 dblp:conf/sbcci/BortolonM17 fatcat:ge6plyg4xrfnjpmluo4frpobti

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

Rasmus Bo Sørensen, Luca Pezzarossa, Martin Schoeberl, Jens Sparsø
2017 Journal of systems architecture  
A NoC for real-time systems needs to support 20 guaranteed-service (GS) channels. Furthermore, many hard real-time applications have multiple modes of operation.  ...  The NoC addresses hard real-time systems and provides guaranteed-service VCs between proces-795 sors.  ... 
doi:10.1016/j.sysarc.2017.02.001 fatcat:i6srzk34p5cp5lhvl3gvj2foqi

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

Waqar Amin, Fawad Hussain, Sheraz Anjum, Sarzamin Khan, Naveed Khan Baloch, Zulqar Nain, Sung Won Kim
2020 IEEE Access  
Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC).  ...  Moreover, the best technique identified in each category based on the evaluation of performance results. INDEX TERMS Network-on-Chip, application mapping, NoC design, VOPD, System-on-Chip.  ...  Therefore, the inherent nondeterministic hard real-time applications could not depend on dynamic mapping.  ... 
doi:10.1109/access.2020.2982675 fatcat:kn6mkit3uvguvc2w6lx5dgddoe

Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

Qaiser Ijaz, El-Bay Bourennane, Ali Kashif Bashir, Hira Asghar
2020 Future Internet  
Open problems are indicated for scientific community as well.  ...  scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy.  ...  The authors would also like to thank Usman Ahmad, Dalhousie University of Canada for his advice on research writing in general.  ... 
doi:10.3390/fi12040064 fatcat:zrt5ergxnvezlmltkbwgiixcm4

Side-channel attack resilience through route randomisation in secure real-time Networks-on-Chip

Leandro Soares Indrusiak, James Harbin, Martha Johanna Sepulveda
2017 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)  
We therefore propose packet route randomisation as a mechanism to increase NoC resilience against side-channel attacks, focusing specifically on the potential impact of such an approach upon hard real-time  ...  Using an evolutionary optimisation approach, we show how to effectively apply route randomisation in such a way that it can increase NoC security while controlling its impact on hard real-time performance  ...  Thus, a hard real-time application Γ comprises n real-time tasks Γ ={τ 1 , τ 2 , . . . , τ n }.  ... 
doi:10.1109/recosoc.2017.8016142 dblp:conf/recosoc/IndrusiakHS17 fatcat:fb75uq3755gwfcu5v35hwuyp4m

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto
2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The proposed methodology is tailored for a reconfigurable hardware architecture based on a flexible communication infrastructure, and exploits applications similarities to obtain an effective mapping.  ...  We also introduce a run-time mapper that is able to introduce new applications that were not known at design-time, preserving the mapping of the original system.  ...  Over the last years, many design-time approaches have been proposed to map multi-core applications on specific communication infrastructures, with a particular emphasis on the emerging NoCs.  ... 
doi:10.1109/tcad.2011.2138140 fatcat:4urkegnggvezrcnijydxpxp7ai

Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip

Andreas Hansson, Martijn Coenen, Kees Goossens
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
In this paper we present a model that enables partial reconfiguration of NoCs and a mapping algorithm that uses the model to map multiple applications onto a NoC with undisrupted Quality-of-Service during  ...  Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip (SoC) communication infrastructure.  ...  Related work Methodologies for dynamic run-time reconfiguration of NoCs are presented in [17, 22] .  ... 
doi:10.1109/date.2007.364416 dblp:conf/date/HanssonCG07 fatcat:mwrfjbe2pjardfnaiqbl6tffda

Key Research Issues for Reconfigurable Network-on-Chip

R. Dafali, J.-Ph. Diguet, M. Sevaux
2008 2008 International Conference on Reconfigurable Computing and FPGAs  
Network on chip (NoC) has emerged as the design paradigm for scalable System on Chip with harsh bandwidth requirements.  ...  Then to deal with the current situation, we introduce a description of a dynamic reconfiguration model for NoC and enumerate several outstanding research issues organized on three topics: dynamic reconfiguration  ...  ReNoC (Reconfigurable Network-on-Chip) [19] NoC architecture viewed by the application as a logical topology built on top of the real physical architecture.  ... 
doi:10.1109/reconfig.2008.72 dblp:conf/reconfig/DafaliDS08 fatcat:p5qskhiec5byvo2zlled4cpcyu
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