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A hard real-time capable multi-core SMT processor
2013
ACM Transactions on Embedded Computing Systems
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Our evaluation shows that the proposed MERASA multi-core provides predictability for hard real-time tasks and also high performance for non hard real-time tasks. ...
Hard real-time applications in safety critical domains require high performance and time analyzability. ...
Marco Paolieri is partially supported by the Catalan Ministry for Innovation, Universities and Enterprise of the Catalan Government and European Social Funds. ...
doi:10.1145/2442116.2442129
fatcat:eqdgv2lcpzcn7neomu7tuz3ma4
T-CREST: Time-predictable multi-core architecture for embedded systems
2015
Journal of systems architecture
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Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. ...
Standard multi-core processors are optimized for the average case and are hardly analyzable. ...
A write-back cache would actually increase the WCET bound, as each cache miss penalty includes a possible cache write-back. ...
doi:10.1016/j.sysarc.2015.04.002
fatcat:yts4coszkbg7vbes3b4hzdyzui
Fault and timing analysis in critical multi-core systems: A survey with an avionics perspective
2018
Journal of systems architecture
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Multi-core processors offer a potential that is promising, but they also suffer from two issues that are only recently being addressed in the safety-critical contexts: lack of methods for assuring timing ...
We consider the classic approach for analyzing the impact of faults in such systems, namely fault injection. ...
Acknowledgments This work was supported by the Swedish Armed Forces, the Swedish Defence Materiel Administration and the Swedish Governmental Agency for Innovation Systems under grant nos. ...
doi:10.1016/j.sysarc.2018.04.001
fatcat:74tk5j6kyjfmxpufn3x7dph6ve
Scope-Aware Data Cache Analysis for WCET Estimation
2011
2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
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Experimental results shows that our proposed analysis obtains up to 74% reduction in the WCET estimates compared to existing data cache analysis. ...
On the other hand, presence of caches, especially data caches, complicates the static worst case execution time (WCET) analysis. ...
In case where no-write-allocate is used (in write-through or write-back policy), a store instruction does not modify the cache state. We consider only load instructions in the cache analysis. ...
doi:10.1109/rtas.2011.27
dblp:conf/rtas/HuynhJR11
fatcat:adoae347djbqhmq7qpdij7wn4y
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
2011
Design, Automation, and Test in Europe
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The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. ...
Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. ...
The modeling of memory hierarchies with multiple levels of caches is critical for practical WCET analysis. ...
doi:10.4230/oasics.ppes.2011.11
dblp:conf/date/SchoeberlSPBP11
fatcat:f3mbwaezuvbeppzfkclo426g2q
A Survey of WCET Analysis of Real-Time Operating Systems
2009
2009 International Conference on Embedded Software and Systems
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WCET tools designed for application program analysis have been applied to analyze RTOS routines by several research groups, but poor WCET estimations have been reported. ...
Traditional WCET analysis mainly deals with application programs and has achieved success in industry. ...
Poor estimations were reported due to the lack of cache modeling in the analysis tool and the difficulty in bounding the loops. ...
doi:10.1109/icess.2009.24
dblp:conf/icess/LvGZDYZ09
fatcat:gtueqpoqy5ew5ptjkunsbx75t4
Unified Cache Modeling for WCET Analysis and Layout Optimizations
2009
2009 30th IEEE Real-Time Systems Symposium
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In this work, we consider the modeling of a generic cache architecture which is most common in commercial processors -separate instruction and data caches in the first level and a unified cache in the ...
Moreover we use our unified cache modeling to develop WCET-driven code and data layout optimizations -where the code and data layout are optimized simultaneously for reducing WCET. ...
Using our cache modeling, we can identify the different sources of WCET over-estimation in a multi-level cache architecture with instruction and data caches. ...
doi:10.1109/rtss.2009.20
dblp:conf/rtss/ChattopadhyayR09
fatcat:7dsnbz2nzzhrreg57ugwbrjbk4
Using polyhedral techniques to tighten WCET estimates of optimized code: A case study with array contraction
2018
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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, cache hierarchies, write policies, cache coherency). ...
They show that for Harris, aiT is still able to derive a WCET estimate without annotations, for all optimization levels except -O1 (at the time of writing, we have no explanation for this observation). ...
doi:10.23919/date.2018.8342142
dblp:conf/date/LefeuvreFCGKPD18
fatcat:67zoygqfanfqtjdmui6cuzavfe
MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding
[chapter]
2017
Lecture Notes in Computer Science
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Caches and multicores are two of the hardware features that have the potential to significantly reduce WCET estimates, yet they pose new challenges on current-practice measurement-based timing analysis ...
In this paper we propose MC2, a technique for multilevel-cache multicores that combines deterministic and probabilistic jitter-bounding approaches to reliably handle both the variability in execution time ...
Our results on a COTS platform confirm that MC2 effectively captures the impact of both multi-level cache variability and inter-core contention in realistic WCET estimates, that tightly upperbound observed ...
doi:10.1007/978-3-319-60588-3_7
fatcat:mcwld7v5pbhnrkyypvmq226pf4
A Survey on Static Cache Analysis for Real-Time Systems
2015
Leibniz Transactions on Embedded Systems
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Then, the discussion is extended to cache analysis in complex execution environment, followed by a survey of existing tools based on static techniques for cache analysis. ...
A vital verification requirement is to estimate the Worst-Case Execution Time (WCET) of programs. These estimates are then used to predict the timing behavior of the overall system. ...
The write-through policy is generally easy to handle in cache analysis, since data writes to a certain cache level incur no change to other cache levels. ...
doi:10.4230/lites-v003-i001-a005
dblp:journals/lites/LvGRW016
fatcat:ax5h3hurpbekjo52thkaduwtki
Complete worst-case execution time analysis of straight-line hard real-time programs
2000
Journal of systems architecture
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On the other hand the high-level analysis addresses the problem of using the results from the low-level to compute the final estimate on the WCET. ...
In this article, the problem of finding a tight estimate on the worst-case execution time (WCET) of a real-time program is addressed. ...
We are also grateful to the members of the department for programming languages and compilers of the University of Paderborn, who provided the compiler which PTA is embedded in. ...
doi:10.1016/s1383-7621(99)00010-7
fatcat:4mzrlanbnjanrnlhhozj5zkrca
Multi-level Unified Caches for Probabilistically Time Analysable Real-Time Systems
2013
2013 IEEE 34th Real-Time Systems Symposium
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In this paper we prove that multi-level cache hierarchies can be used in the context of Probabilistic Timing Analysis and tight WCET estimates can be obtained. ...
Our results show that the probabilistic WCET (pWCET) estimates provided by our analysis technique effectively benefit from having multi-level caches. ...
-Therefore, there is a need for low-cost industrial-viable means to determine trustworthy and tight Worst-Case Execution Time (WCET) estimates in the presence of multi-level caches. ...
doi:10.1109/rtss.2013.43
dblp:conf/rtss/KosmidisAQC13
fatcat:6nxuac3owfculhavh5p32ye4fm
Design of a WCET-Aware C Compiler
2006
2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia
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It opens up new possibilities for the design of WCET-aware optimizations in the future. ...
The work described in this paper is smoothly integrated into a C compiler environment for the Infineon TriCore processor. ...
This requires some kind of back annotation of the WCET data stored in the LLIR up to our high-level IR. ...
doi:10.1109/estmed.2006.321284
dblp:conf/estimedia/FalkLT06
fatcat:gwwwsls7xzbkljj5x7k55jeuim
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach
2017
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017
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In this paper we give an overview of the objectives of ARGO and explore the challenges introduced by our approach. ...
Parallel architectures are nowadays not only confined to the domain of high performance computing, they are also increasingly used in embedded time-critical systems. ...
Code-level and system-level WCET analysis Code-level and system-level WCET analysis jointly calculate the multi-core WCET for the target architectures. ...
doi:10.23919/date.2017.7927000
dblp:conf/date/DerrienPABBDDDF17
fatcat:7d3ac4uwwrb6llwboieuajjuqu
Design and integration of hierarchical-placement multi-level caches for real-time systems
2018
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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For this type of caches, we explore and propose different multi-level cache setups. ...
However, caches heavily complicate timing analysis due to hard-to-predict access patterns, with few works dealing with time analyzability of multi-level cache hierarchies. ...
The L2 is write-back write-allocate, so on a store miss, the cache line is fetched into L2 -and modified. ...
doi:10.23919/date.2018.8342052
dblp:conf/date/BenedicteHAC18
fatcat:ku7eyenxa5cffgs7mh5nqvtfpm
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