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HMC: Model Checking for Hardware Memory Models [article]

Michalis Kokologiannakis, Viktor Vafeiadis
2019 Zenodo  
This is the artifact accompanying the paper "HMC: Model Checking for Hardware Memory Models" which will appear on ASPLOS20.  ...  We consider our paper's artifact to be the set of benchmarks we used in the paper, as well as the results we got by running particular versions of model checking tools (GenMC, HMC, Nidhugg, Herd, rmem,  ...  The artifact (available on Zenodo) consists of a Virtual Machine (VM) containing binaries for all the model checking tools used, along with all the benchmarks used in the submitted version of our paper  ... 
doi:10.5281/zenodo.3562083 fatcat:7gpxxdbyw5cg7lkkh3m2fuxeza

Enabling energy efficient Hybrid Memory Cube systems with erasure codes

Shibo Wang, Yanwei Song, Mahdi Nazm Bojnordi, Engin Ipek
2015 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)  
The Hybrid Memory Cube (HMC) is a promising alternative to DDRx memory due to its potential to achieve significantly higher bandwidth.  ...  Inaccessible data stored in a sleeping HMC module can be reconstructed by decoding related data retrieved from other active HMCs, rather than waiting for the sleeping HMC module to become active.  ...  The power overhead of the additional hardware represents less than 0.03% of the entire power-capped HMC system. The latencies are correctly modeled as processor cycles for performance analysis.  ... 
doi:10.1109/islped.2015.7273492 dblp:conf/islped/WangSBI15 fatcat:iigykddxgzgujnng3xvjyqp7ny

In-Memory Data Rearrangement for Irregular, Data-Intensive Computing

Scott Lloyd, Maya Gokhale
2015 Computer  
Our results on representative irregular benchmarks using the Micron Hybrid Memory Cube memory model show speedup, bandwidth savings, and energy reduction in all cases.  ...  Unlike other proposed processingin-memory architectures, the rearrangement hardware performs data reduction, not compute offload.  ...  We thank Roger Pearce for the original pagerank benchmark.  ... 
doi:10.1109/mc.2015.230 fatcat:56h5aajgz5dh3d4wvfm5rg44oe

CAIRO

Ramyad Hadidi, Lifeng Nai, Hyojong Kim, Hyesoon Kim
2017 ACM Transactions on Architecture and Code Optimization (TACO)  
and decision model for enabling instruction-level offloading of PIM without any burden on programmers.  ...  Several memory vendors have also started to integrate computation logics into the memory, such as Hybrid Memory Cube (HMC), the latest version of which supports up to 18 in-memory atomic instructions.  ...  ACKNOWLEDGMENTS The authors thank the anonymous reviewers for their valuable comments. We also thank Sandia National Labs for providing the SST/VaultSim framework.  ... 
doi:10.1145/3155287 fatcat:ygfptqn265fgphtob733sorfvq

Practical Near-Data Processing for In-Memory Analytics Frameworks

Mingyu Gao, Grant Ayers, Christos Kozyrakis
2015 2015 International Conference on Parallel Architecture and Compilation (PACT)  
(HMC) High Bandwidth Memory (HBM) Figs: www.extremetech.com Base NDP Hardware Vau lt Logic NoC Logic Die DRAM Die ...  ...  , … Lightweight hardware structures and software runtime Shared Memory Model  Unified physical address space across stacks o Direct access from any NDP/host core to memory in any vault/stack  ... 
doi:10.1109/pact.2015.22 dblp:conf/IEEEpact/GaoAK15 fatcat:f5xuexzekzfl7h62fnpje6gfga

A Low Power Consuming Model of Parallel Programming for HPC System

Mohammed Nawaf Altouri, Abdullah M.
2019 International Journal of Advanced Computer Science and Applications  
Moreover, the HMC model was evaluated by implementing the matrix multiplication benchmarking application. Consequently, it can be considered a leading model for the emerging Exascale computing system.  ...  In the current study, we have proposed a Hybrid MVAPICH-2 + CUDA (HMC) parallel programming model that outperformed other state-of-the-art dual and tri hierarchy level approaches with respect to power  ...  Random Direct Memory Access (RDMA) is hardware architecture we used to implement our hybrid model. It is especially useful in massively parallel computer clusters.  ... 
doi:10.14569/ijacsa.2019.0100522 fatcat:w2b4ipipprc3hpr3grl5f44knu

tfp.mcmc: Modern Markov Chain Monte Carlo Tools Built for Modern Hardware [article]

Junpeng Lao, Christopher Suter, Ian Langmore, Cyril Chimisov, Ashish Saxena, Pavel Sountsov, Dave Moore, Rif A. Saurous, Matthew D. Hoffman, and Joshua V. Dillon
2020 arXiv   pre-print
We also thank Alexey Radul and Ashok Popat for their review of this work.  ...  -The remaining computation is dominated by U-turn checking. Various checks require a history of samples (made finite as implied by the first point).  ...  Case Study: HMC Preserving vectorized computation for Hamiltonian Monte Carlo (HMC, [Neal 2011] ) and other similarly "simple" Metropolis-Hastings [Hastings 1970 ] samplers is generally straightforward  ... 
arXiv:2002.01184v1 fatcat:szsdpthxvjbbbbduisykwfpyd4

A Survey of Resource Management for Processing-In-Memory and Near-Memory Processing Architectures

Kamil Khan, Sudeep Pasricha, Ryan Gary Kim
2020 Journal of Low Power Electronics and Applications  
Therefore, designing intelligent resource management techniques for computation offloading is vital for leveraging the potential offered by this new paradigm.  ...  random-access memory (DRAM).  ...  The actual choice of the vault and RVU is made after checking for data dependencies between instructions.  ... 
doi:10.3390/jlpea10040030 fatcat:yzpcli2ynfe4hbfpabvwinn2fi

InvisiMem

Shaizeen Aga, Satish Narayanasamy
2017 SIGARCH Computer Architecture News  
A practically feasible low-overhead hardware design that provides strong defenses against memory bus side channel remains elusive.  ...  CCS CONCEPTS • Security and privacy → Hardware-based security protocols; • Hardware → 3D integrated circuits;  ...  We thank Mohit Tiwari and anonymous reviewers for their comments which helped improve this paper. We also thank Sriram Rajamani for the valuable discussions.  ... 
doi:10.1145/3140659.3080232 fatcat:56pwkqil3be73hcfgrhgvttzii

A Survey on Graph Processing Accelerators: Challenges and Opportunities [article]

Chuangyi Gui, Long Zheng, Bingsheng He, Cheng Liu, Xinyu Chen, Xiaofei Liao, Hai Jin
2019 arXiv   pre-print
Despite a wealth of existing efforts on developing graph processing systems for improving the performance and/or energy efficiency on traditional architectures, dedicated hardware solutions, also referred  ...  Interestingly, we find that there is not an absolute winner for all three aspects in graph acceleration due to the diverse characteristics of graph processing and complexity of hardware configurations.  ...  For supporting large graphs, an intuitive method is to extend to use larger memory for storing the whole graph. For example, we can use a cluster network of HMCs.  ... 
arXiv:1902.10130v1 fatcat:p5lzlf3gubckfpu4eowgo4myi4

Retrofitting the IBM POWER Hypervisor to Support Mandatory Access Control

Enriquillo Valdez, Reiner Sailer, Ronald Perez
2007 Twenty-Third Annual Computer Security Applications Conference (ACSAC 2007)  
In this paper, we describe the design and implementation of a Hypervisor-based Mandatory Access Control (MAC) that achieves policy-driven distributed workload isolation for the IBM Power Hypervisor (PHYP  ...  We would also like to thank Paul Karger for his comments on previous MAC work on hypervisors.  ...  The authors would like to thank the IBM POWER Design and Development Team for providing access to PHYP information and platforms.  ... 
doi:10.1109/acsac.2007.43 dblp:conf/acsac/ValdezSP07 fatcat:mx4qvbzoezbgtd6eujal26jq5q

Retrofitting the IBM POWER Hypervisor to Support Mandatory Access Control

Enriquillo Valdez, Reiner Sailer, Ronald Perez
2007 Proceedings of the Computer Security Applications Conference  
In this paper, we describe the design and implementation of a Hypervisor-based Mandatory Access Control (MAC) that achieves policy-driven distributed workload isolation for the IBM Power Hypervisor (PHYP  ...  We would also like to thank Paul Karger for his comments on previous MAC work on hypervisors.  ...  The authors would like to thank the IBM POWER Design and Development Team for providing access to PHYP information and platforms.  ... 
doi:10.1109/acsac.2007.4412991 fatcat:r7mii3l2kjf3blblac6cjc5pcm

A scalable processing-in-memory accelerator for parallel graph processing

Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi
2015 SIGARCH Computer Architecture News  
It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model.  ...  However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem.  ...  Acknowledgments We thank the anonymous reviewers for their valuable feedback.  ... 
doi:10.1145/2872887.2750386 fatcat:s73lzobpobfb7mem6e2m5xcmci

A scalable processing-in-memory accelerator for parallel graph processing

Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi
2015 Proceedings of the 42nd Annual International Symposium on Computer Architecture - ISCA '15  
It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model.  ...  However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem.  ...  Acknowledgments We thank the anonymous reviewers for their valuable feedback.  ... 
doi:10.1145/2749469.2750386 dblp:conf/isca/AhnHYMC15 fatcat:yxk4mj22h5bkdozvbfxloj3qyi

A generic processing in memory cycle accurate simulator under hybrid memory cube architecture

Geraldo F. Oliveira, Paulo C. Santos, Marco A. Z. Alves, Luigi Carro
2017 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
The SystemC Programming Model Hardware Description Languages (HDLs), like Verilog and VHDL, have significantly increased the productivity level for hardware designers by creating a modeling environment  ...  However, with the growth in complexity in modern hardware systems, the modeling platform employed would also need to be elevated its abstraction level.  ... 
doi:10.1109/samos.2017.8344611 dblp:conf/samos/OliveiraSAC17 fatcat:empp6u2hpvbgfl7gfh4xbjtkhi
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