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TERAFLUX: Harnessing dataflow in next generation teradevices

Roberto Giorgi, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Rahul Gayatri, Sylvain Girbal, Daniel Goodman (+17 others)
2014 Microprocessors and microsystems  
Our platform comprises 1000+ general purpose cores per chip in order to properly explore the above challenges.  ...  Three major challenges have been identified: programmability, manageable architecture design, and reliability.  ...  Behram's research interests include many-core architectures, and Software and Hardware Transactional Memory. His contact email address is  ... 
doi:10.1016/j.micpro.2014.04.001 fatcat:x7zxfxtuxrdvrf67fbljcqiqee

Harnessing cross-layer-design

Ismet Aktas, Muhammad Hamad Alizai, Florian Schmidt, Hanno Wirtz, Klaus Wehrle
2014 Ad hoc networks  
Essentially, protocols at each layer have a very specific task and they need to fulfill this task independently.  ...  A prominent example is TCP's performance drop in wireless networks as it misinterprets packet loss, due to poor link conditions, as congestion in the network.  ...  fact the core property of a protocol.  ... 
doi:10.1016/j.adhoc.2013.09.003 fatcat:2bjsppdhqjcmpgthrfrjtrkaf4

HARNESS and fault tolerant MPI

Graham E Fagg, Antonin Bukovsky, Jack J Dongarra
2001 Parallel Computing  
Also discussed is the experimental HARNESS core (G_HCORE) implementation that FT-MPI is built to operate upon. Ó  ...  As current HPC systems increase in size with greater potential levels of individual node failure, the need arises for new fault tolerant systems to be developed.  ...  The core calls the code as a function, or a program uses the core as a runtime library to load the function, which it then calls directly itself. · Indirect invocation.  ... 
doi:10.1016/s0167-8191(01)00100-4 fatcat:6mvh7mragrghfai5tasa3rftwu

Harnessing Adaptivity Analysis for the Automatic Design of Efficient Embedded and HPC Systems

Silvia Lovergine, Fabrizio Ferrandi
2013 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum  
Such a scheduling technique, called dynamic AC-scheduling, provides support for the High-Level Synthesis (HLS) of adaptive hardware cores.  ...  In other words, designing modern supercomputers, as well as modern embedded systems, requires a holistic approach that relies on tightly coupled hardware-software co-design methodologies.  ...  Hardware Cores with Support for Adaptive Execution This Section presents a novel architectural model for adaptive embedded systems.  ... 
doi:10.1109/ipdpsw.2013.230 dblp:conf/ipps/LovergineF13 fatcat:vpdgybp2gnbmve6wzgscv6hqoa

Browser-based Harnessing of Voluntary Computational Power

Tomasz Fabisiak, Arkadiusz Danilecki
2017 Foundations of Computing and Decision Sciences  
We survey the techniques employing the idea of browser-based voluntary computing (BBVC), discuss their commonalities, recognize recurring problems and their solutions and finally we describe a prototype  ...  Software bugs may inadvertently harm users' machines, and faulty hardware or software errors on users' machines may be indistinguishable from intentionally submitted wrong results.  ...  MLitB architecture have separate master and data servers. Master server may host many machine learning projects.  ... 
doi:10.1515/fcds-2017-0001 fatcat:mvtpvz4txvgphcfaqcdsfw6mgy

Harnessing Green IT: Principles and Practices

San Murugesan
2008 IT Professional Magazine  
applications, Web engineering, e-business and IT for emerging markets.  ...  He also edits and contributes to the IT in Emerging Markets Department of IT Professional .H e is a Fellow of the Australian Computer Society, a Fellow of IETE, a Senior Member of IEEE and a distinguished  ...  We would also like to thank Souleiman Hasan and Gabriel Costello for their assistance.  ... 
doi:10.1109/mitp.2008.10 fatcat:g5np2vq245drvflci2bc7bj4me

Green Software [chapter]

Bob Steigerwald, Abhishek Agrawal
2012 Harnessing Green It  
We would also like to thank Souleiman Hasan and Gabriel Costello for their assistance.  ...  We profusely thank Simon Liu, Editor-in-Chief of the IEEE Computer Society's IT Professional magazine, for writing a foreword to this book.  ...  Green software can be classified into four broad categories: • Software that is greener -consumes less energy to run; • Embedded software that assists other things in going green (smart operations); •  ... 
doi:10.1002/9781118305393.ch3 fatcat:epohredblvhg5ei2chbw2fmhpy

HARNESS fault tolerant MPI design, usage and performance issues

Graham E. Fagg, Jack J. Dongarra
2002 Future generations computer systems  
Subsequently forcing them to support a dynamic process model suitable for use on clusters or distributed systems would have reduced their performance.  ...  This is especially true when MPI implementations are used as the communication media for GRID applications where the GRID architectures themselves are inherently unreliable thus requiring new fault tolerant  ...  The core calls the code as a function, or a program uses the core as a runtime library to load the function, which it then calls directly itself. • Indirect invocation.  ... 
doi:10.1016/s0167-739x(02)00090-0 fatcat:fr2gymnxzjaetmra4bs67tiatq

The Machine Learning Bazaar: Harnessing the ML Ecosystem for Effective System Development [article]

Micah J. Smith, Carles Sala, James Max Kanter, Kalyan Veeramachaneni
2019 arXiv   pre-print
First, we introduce ML primitives, a unified API and specification for data processing and ML components from different software libraries.  ...  To address these problems, we introduce the Machine Learning Bazaar, a new approach to developing machine learning and automated machine learning software systems.  ...  core ML Bazaar software libraries such as MLPrimitives and MLBlocks.  ... 
arXiv:1905.08942v3 fatcat:7m7urx74hrfvdjgrgo6ttyjn6y

Harnessing the Full Potential of Industrial Demand-Side Flexibility: An End-to-End Approach Connecting Machines with Markets through Service-Oriented IT Platforms

Martin Roesch, Dennis Bauer, Leon Haupt, Robert Keller, Thomas Bauernhansl, Gilbert Fridgen, Gunther Reinhart, Alexander Sauer
2019 Applied Sciences  
It consists of a business-individual company-side platform, where suitable services for energy-oriented manufacturing are offered.  ...  Industrial demand-side response presents a promising way to balance energy supply and consumption. For this, energy demand is flexibly adapted based on external incentives.  ...  In line with the increasing digitization, cyber-physical systems, which merge the physical and virtual world through embedded hardware and software, present a new approach [54] [55] [56] .  ... 
doi:10.3390/app9183796 fatcat:2romg4ct3vddhmclnfa26m6iiy

A context saving fault tolerant approach for a shared memory many-core architecture

Eduardo Wachter, Nicolas Ventroux, Fernando G. Moraes
2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS)  
Mechanisms for runtime fault-tolerance in manycore architectures are mandatory to cope with transient and permanent faults.  ...  This technique is implemented on an embedded multicore architecture named P2012.  ...  Software Stack The software stack is named HARS [10] and it is based on a hardware-assisted runtime software.  ... 
doi:10.1109/iscas.2015.7168947 dblp:conf/iscas/WachterVM15 fatcat:4m7mdwki3je3jkmnaspnv3ko34

Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality

2018 Proceedings of the IEEE  
SLAM algorithmic approaches, and (4) tools for delivering, where appropriate, accelerated, adaptive SLAM solutions in a managed, JIT-compiled, adaptive runtime context.  ...  This paper describes the results of a major research effort to assemble the algorithms, architectures, tools, and systems software needed to enable delivery of SLAM, by supporting applications specialists  ...  A hybrid scheduling technique is introduced called power-aware code generation, which is a compiler-based approach to runtime power management for heterogeneous cores (Section III-C). 3) Computer Architecture  ... 
doi:10.1109/jproc.2018.2856739 fatcat:a66m7lzvn5bjvlxyw7qkd2qaky

Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach

C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J. M. Zins (+14 others)
2011 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)  
on portable byte-code, run-time resource management policies and mechanisms as well as design space exploration methodologies for Many-core computing architectures.  ...  The 2PARMA project aims at overcoming the lack of parallel programming models and run-time resource management techniques to exploit the features of many-core processor architectures.  ...  a new framework for supporting the QoS-based runtime management of a generic many-core computing platform.  ... 
doi:10.1109/recosoc.2011.5981522 dblp:conf/recosoc/SilvanoFCAPZBCCSMZHSBPRYABSKAAMV11 fatcat:gco2jm23l5gojnmo5jqkspxpze

Methodologies for the WCET Analysis of Parallel Applications on Many-Core Architectures

Vincent Nelis, Patrick Meumeu Yomsi, Luis Miguel Pinho
2015 2015 Euromicro Conference on Digital System Design  
After discussing the pros and cons of all different methodologies for WCET analysis, we introduce a new approach that is developed within the P-SOCRATES project.  ...  After discussing the pros and cons of all different methodologies for WCET analysis, we introduce a new approach that is developed within the P-SOCRATES project.  ...  ACKNOWLEDGEMENTS This work was partially supported by National Funds through FCT/MEC (Portuguese Foundation for Science and Technology) and when applicable, co-financed by ERDF (  ... 
doi:10.1109/dsd.2015.105 dblp:conf/dsd/NelisYP15 fatcat:e3swrmvesnewzeranon3e7c7uy

Hybrid multi-core architecture for boosting single-threaded performance

Jun Yan, Wei Zhang
2007 SIGARCH Computer Architecture News  
be exploited to deal with the runtime events that are typically difficult for the VLIW core to handle, such as L2 cache misses.  ...  While multithreaded applications can naturally leverage the enhanced throughput of multi-core processors, a large number of important applications are single-threaded, which cannot automatically harness  ...  The proposed hybrid architecture can also be potentially very useful for high-performance embedded applications.  ... 
doi:10.1145/1241601.1241603 fatcat:vjzotxsbo5dtvc6oe6wcifxcie
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