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Guaranteeing Performance Yield in High-Level Synthesis

W.-l. Hung, Xiaoxia Wu, Yuan Xie
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
In this paper, we present a variation-aware performance yield-guaranteed high-level synthesis algorithm.  ...  Current high-level synthesis tools, performing task scheduling, resource allocation and binding, may result in unexpected performance discrepancy due to the ignorance of the impact of process variation  ...  PERFORMANCE YIELD-GUARANTEED HIGH-LEVEL SYNTHESIS In this section, a new high-level synthesis (HLS) framework is proposed to improve the performance yield of a design under process variation.  ... 
doi:10.1109/iccad.2006.320050 fatcat:pt6jnqav2nf65gyze25ax3i2ne

Guaranteeing performance yield in high-level synthesis

W.-L. Hung, Xiaoxia Wu, Yuan Xie
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
In this paper, we present a variation-aware performance yield-guaranteed high-level synthesis algorithm.  ...  Current high-level synthesis tools, performing task scheduling, resource allocation and binding, may result in unexpected performance discrepancy due to the ignorance of the impact of process variation  ...  PERFORMANCE YIELD-GUARANTEED HIGH-LEVEL SYNTHESIS In this section, a new high-level synthesis (HLS) framework is proposed to improve the performance yield of a design under process variation.  ... 
doi:10.1145/1233501.1233561 dblp:conf/iccad/HungWX06 fatcat:unorhpxrmvhz7nzqidlxcix5oi

A variation aware high level synthesis framework

Feng Wang, Guangyu Sun, Yuan Xie
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
In this paper, we propose a high level synthesis framework to take into account of the performance/power variation for function units.  ...  An efficient performance/power yield perturbation computation method for DFG significantly improves the effectiveness of our yield driven high level synthesis algorithm.  ...  YIELD DRIVEN HIGH LEVEL SYNTHESIS In this section, we first present the yield driven high level synthesis framework.  ... 
doi:10.1145/1403375.1403630 fatcat:hatwbjivlrhpnm7h5crouw22ge

Probabilistic robust linear quadratic regulators with Gaussian processes [article]

Alexander von Rohr, Matthias Neumann-Brosig, Sebastian Trimpe
2021 arXiv   pre-print
While learning-based control has the potential to yield superior performance in demanding applications, robustness to uncertainty remains an important challenge.  ...  The formulation is based on a recently proposed algorithm for linear quadratic control synthesis, which we extend by giving probabilistic robustness guarantees in the form of credibility bounds for the  ...  This work was supported in part by the Cyber Valley Initiative and the Max Planck Society.  ... 
arXiv:2105.07668v1 fatcat:atnzxokb5bberfqv5co6v53aia

Variability-driven module selection with joint design time optimization and post-silicon tuning

Feng Wang, Xiaoxia Wu, Yuan Xie
2008 2008 Asia and South Pacific Design Automation Conference  
Traditional module selection techniques in high level synthesis use worst case delay/power information to perform the optimization, and therefore may be too pessimistic such that extra resources are used  ...  To the best of our knowledge, this is the first variability-driven high level synthesis technique that considers post-silicon tuning during design time optimization. 1  ...  module selection step in high level synthesis.  ... 
doi:10.1109/aspdac.2008.4483963 dblp:conf/aspdac/WangWX08 fatcat:dno7zrce2ngk5m5tsvetyvmd4u

Automatic Hardware Synthesis from Specifications: A Case Study

Roderick Bloem, Stefan Galler, Barbara Jobstmann, Nir Piterman, Amir Pnueli, Martin Weiglhofer
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
We propose to use a formal specification language as a high-level hardware description language.  ...  in PSL.  ...  Acknowledgments This work was supported in part by the European Commission under contract number 507219 (PROSYD).  ... 
doi:10.1109/date.2007.364456 fatcat:le76okqzjbgcvbh5tvefvl2ew4

Microgravity Isolation System Design: A Case Study

R. David Hampton, Carl R. Knospe, Carlos M. Grodsinsky
1996 Journal of Spacecraft and Rockets  
The purpose of including this high noise-contamination level was to bias the extended I-I.z-synthesis machinery to place much greater "confidence" in the acceleration signal, and therefore to give it preeminence  ...  The structured uncertainty test (which implies no cross-coupling between sensor channels) yielded guarantees on stability for variations in the sensors which were quite large.  ... 
doi:10.2514/3.55716 fatcat:3mqyvttwmvgdrgzpqy365v4nfi

A new versatile linker for the solid-phase synthesis of secondary amines

Heiko Glatz, Willi Bannwarth
2003 Tetrahedron Letters  
The feasibility was demonstrated in the parallel synthesis of a small set of different secondary amines.  ...  A novel linker for the solid-phase synthesis of secondary amines based on an intramolecular cyclization was developed.  ...  a high level of purity of released secondary amines.  ... 
doi:10.1016/s0040-4039(02)02478-4 fatcat:oqdmr3ssvjdtnewkvlnz5zltem

Automated exploration of datapath and unrolling factor during power–performance tradeoff in architectural synthesis using multi-dimensional PSO algorithm

Anirban Sengupta, Vipul Kumar Mishra
2014 Expert systems with applications  
A novel algorithm for automated simultaneous exploration of datapath and Unrolling Factor (UF) during power-performance tradeoff in High Level Synthesis (HLS) using multi-dimensional particle swarm optimization  ...  most cases; (c) balancing the tradeoff between power-performance metrics as well as control states and execution delay during loop unrolling; (d) sensitivity analysis of PSO parameter such as swarm size  ...  LegUp is able to synthesize C language to hardware, thereby providing a useful platform to perform high level synthesis.  ... 
doi:10.1016/j.eswa.2014.01.041 fatcat:vziobdi57fgfdlasviytyichqu

Death, taxes and failing chips

Chandu Visweswariah
2003 Proceedings of the 40th conference on Design automation - DAC '03  
This invited paper discusses the methodology, analysis, synthesis and modeling aspects of this problem.  ...  These aspects of the problem are compared and contrasted in the ASIC and custom (microprocessor) domains.  ...  However, it will have a profound impact on the modeling, analysis, verification, synthesis and methodology of high-performance integrated circuits.  ... 
doi:10.1145/775919.775921 fatcat:i7wwbis2urehjc62byywgik3ya

Death, taxes and failing chips

Chandu Visweswariah
2003 Proceedings of the 40th conference on Design automation - DAC '03  
This invited paper discusses the methodology, analysis, synthesis and modeling aspects of this problem.  ...  These aspects of the problem are compared and contrasted in the ASIC and custom (microprocessor) domains.  ...  However, it will have a profound impact on the modeling, analysis, verification, synthesis and methodology of high-performance integrated circuits.  ... 
doi:10.1145/775832.775921 dblp:conf/dac/Visweswariah03 fatcat:dmneezinb5dtngemzqesgrph5e

Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies

Georges G.E. Gielen
2007 2007 Asia and South Pacific Design Automation Conference  
This invited paper describes progress in modeling techniques for design and verification of complex integrated systems, in circuit and yield optimization tools for analog/RF circuits, as well as in signal  ...  However, scaling into the nanometer era also brings problems of leakage power, increasing variability and degradation, reducing supply voltages and worsening signal integrity conditions, all this in combination  ...  Other recent work uses cell-level synthesis to built statistical trade-off curves that "guarantee" some prescribed yield level for a given performance level [27] .  ... 
doi:10.1109/aspdac.2007.358024 dblp:conf/aspdac/Gielen07 fatcat:nmg3jf2h7zbyxe5joafirfz724

A variation-tolerant scheduler for better than worst-case behavioral synthesis

Jason Cong, Albert Liu, Bin Liu
2009 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09  
Then we propose the BTW scheduler, a 0-1 integer linear programming (ILP) scheduling algorithm with the objective of minimizing the expected latency, to provide a high-level synthesis aid for the stallable-FSM  ...  There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems.  ...  In Synchronous designs, variation awareness is particularly relevant for high-level synthesis (HLS).  ... 
doi:10.1145/1629435.1629467 dblp:conf/codes/CongLL09 fatcat:6xizno3twvh7xe5uled3nnypg4

Comparison of Different Multivariable Control Design Methods Applied on Half Car Test Setup

David Vaes, Kris Smolders, Jan Swevers, Paul Sas
2006 European Journal of Control  
The tracking performance of the controller designs based on static or dynamic decoupling is comparable with the performance of the controller based on -synthesis.  ...  This article compares three MIMO feedback control design procedures with respect to design complexity and obtained performance: (1) DK-iteration, the most common -synthesis method to design robust MIMO-controllers  ...  and yields unnecessary high order controllers.  ... 
doi:10.3166/ejc.12.307-324 fatcat:mmaytsbcqbfennnonsmdkaku2y

Building Verifiable Sensing Applications Through Temporal Logic Specification [chapter]

Asad Awan, Ahmed Sameh, Suresh Jagannathan, Ananth Grama
2007 Lecture Notes in Computer Science  
To address these issues, we propose a novel and high-level programming model that directly exposes control over sensor network behavior using temporal logic specifications, in conjunction with a set of  ...  The synthesis engine generates specifications in TLA+, which are compiled down to sensor node primitive actions.  ...  In contrast, we present a high-level programming model for sensor network programming in which program behavior is expressed as invariants that directly capture performance and resource constraints.  ... 
doi:10.1007/978-3-540-72584-8_157 fatcat:bzu4fxllvbhmngy3sg6zdxngmy
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