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DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

Haririan
2020 Computers  
Dealing with resource constraints is an inevitable feature of embedded systems. Power and performance are the main concerns beside others.  ...  To that end, they entail an effective collaboration between software and hardware. A case review in the end wraps up the discussed topics.  ...  Section 5 reviews a case in which complex embedded systems-running mixed-criticality tasks-are explored via a virtual framework equipped with a run-time power management mechanism.  ... 
doi:10.3390/computers9010002 fatcat:4updttelvjadxlsk2xqmc2spt4

Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems

Michel Kinsy, Omer Khan, Ivan Celanovic, Dusan Majstorovic, Nikola Celanovic, Srinivas Devadas
2011 2011 IEEE 32nd Real-Time Systems Symposium  
This approach yields real-time execution on the order of 1μs simulation time step (including input/output latency) for a broad class of power electronics converters.  ...  The more extensive use of computation, sensing, and communication, tightly coupled with power processing, calls for a fundamental reassessment of some of the prevailing paradigms in the real-time control  ...  PROPOSED HARDWARE MULTICORE ARCHITECTURE For power electronics, traditional approaches using offthe-shelf single core or multicore general-purpose processor or FPGA's (Field Programmable Gate Array), are  ... 
doi:10.1109/rtss.2011.35 dblp:conf/rtss/KinsyKCMCD11 fatcat:p5g4mwqlcbgpvovedevvjpqtyq

Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards [article]

Rajeev Muralidhar and Renata Borovica-Gajic and Rajkumar Buyya
2020 arXiv   pre-print
Many research surveys have covered different aspects of techniques in hardware and microarchitecture across devices, servers, HPC, data center systems along with software, algorithms, frameworks for energy  ...  These trends continue, arguably with other limits, along with challenges imposed by tighter integration, extreme form factors and diverse workloads, making systems more complex from an energy efficiency  ...  This tool thereby allows architects to estimate power of future generation designs early in the design phase. McPAT [73] can simulate timing, area and power of multicore processors.  ... 
arXiv:2007.09976v2 fatcat:enrfj2qgerhyteapwykxcb5pni

Energy Efficient and Fault Tolerant Multicore Wireless Sensor Network: E²MWSN

Hong-Ling Shi, Kun Mean Hou, Hai-Ying Zhou, Xing Liu
2011 2011 7th International Conference on Wireless Communications, Networking and Mobile Computing  
Comparing with multicore system, the unicore WSN node system has further execution time and higher energy consumption.  ...  SoC 7.2.1.2.2.Different cells(4-bit, 8-bit, 16-bit, 32-bit) Safe Gate Input Switch Safe Gate Input Switch I O O I I O Sensor Control SoC C C Nano Risc Nano Risc  ...  System services include basic types and definitions, software timers, default configuration parameters, encryption module access, etc.  Application services include modules that are not required by the  ... 
doi:10.1109/wicom.2011.6040317 fatcat:b6qehpnmxjd35go7ycy5v5ru5y

Optimization and deployment of CNNs at the edge

Paolo Meloni, Luca Benini, Maura Pintor, Battista Biggio, Bernhard Moser, Natalia Shepeleva, Nikos Fragoulis, Ilias Theodorakopoulos, Michael Masin, Francesca Palumbo, Daniela Loi, Paola Busia (+6 others)
2019 Proceedings of the 16th ACM International Conference on Computing Frontiers - CF '19  
ALOHA considers hardware-related variables and security, power efficiency, and adaptivity aspects during the Permission to make digital whole development process, from pre-training hyperparameter optimization  ...  time and power consumption.  ...  time needed to implement the baseline and the modified model on NEURAghe, configured on a Xilinx Zynq Z-7010 SoC.  ... 
doi:10.1145/3310273.3323435 dblp:conf/cf/MeloniLBDPSSM0B19 fatcat:axfii7pnincxvkvxyxtub6nhpm

On-Device Deep Learning Inference for System-on-Chip (SoC) Architectures

Tom Springer, Elia Eiroa-Lledo, Elizabeth Stevens, Erik Linstead
2021 Electronics  
The results indicate that our proposed resource management framework can be leveraged to facilitate integration of machine learning algorithms with real-time operating systems and embedded platforms, including  ...  The practicality of our scheduling framework was demonstrated by integrating it into a commercial real-time operating system (VxWorks) then running a typical deep learning image processing application  ...  However, SoC-type devices typically consist of multicore-based architectures.  ... 
doi:10.3390/electronics10060689 fatcat:efmsvkcg3rg3lk6tkk7txtx3uu

Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip

David Atienza, Emilio Martinez
2009 2009 IEEE Computer Society Annual Symposium on VLSI  
Then, a thermal management unit and clock frequency controllers adjust the frequency and voltage of the processing elements according to the temperature requirements at run-time.  ...  We show experimental results of the infrastructure to implement effective global temperature control policies for a real-life 4-core MPSoC, emulated on an FPGA-based emulation framework.  ...  Experimental Results From our experiments we first report the run-time thermal evolution of the MPSoC case study while executing multiple instances of the parallel VTC software application.  ... 
doi:10.1109/isvlsi.2009.25 dblp:conf/isvlsi/AtienzaM09 fatcat:tag63kk4lncszm6od2i62oyatq

Systematic Approach for State-of-the-Art Architectures and System-on-chip Selection for Heterogeneous IoT Applications

Ramesh Krishnamoorthy, Kalimuthu Krishnan, Bharatiraja Chokkalingam, Sanjeevikumar Padmanaban, Zbigniew Leonowicz, Jens Bo Holm-Nielsen, Massimo Mitolo
2021 IEEE Access  
The outcome of SoCs attained through the GA are tested by analyzing their execution time and performance using various evaluation benchmarks.  ...  The various instructions set architectures (ISA) are implemented in a Zynq-7000 (xc7Zz20clg484-1) FPGA device to examine the feasibility of design space requirements for real-time hardware execution.  ...  Maryam et al. had proposed a low-cost instruction pre-fetching scheme with ultra-low power multicore processors.  ... 
doi:10.1109/access.2021.3055650 fatcat:n5yo3savcjdyxdolpwrlc5dza4

Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node [article]

Alfio Di Mauro, Francesco Conti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini
2020 arXiv   pre-print
In this work, we introduce the first fully programmable IoT end-node system-on-chip (SoC) capable of executing software-defined, hardware-accelerated BNNs at ultra-low voltage.  ...  Our SoC exploits a hybrid memory scheme where error-vulnerable SRAMs are complemented by reliable standard-cell memories to safely store critical data under aggressive voltage scaling.  ...  Chip Implementation Quentin SoC at the system level. For example, SRAMs and SMCs can be independently power-gated.  ... 
arXiv:2007.08952v1 fatcat:wj5ecbpaejb7dimlbbz3maomjy

Hardware/software co-design for energy-efficient seismic modeling

Jens Krueger, David Donofrio, John Shalf, Marghoob Mohiyuddin, Samuel Williams, Leonid Oliker, Franz-Josef Pfreund
2011 Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis on - SC '11  
We have developed an FPGA-accelerated architectural simulation platform to accurately model the power and performance of the Green Wave design.  ...  Results show that across highly-tuned high-order RTM stencils, the Green Wave implementation can offer up to 8× and 3.5× energy efficiency improvement per node respectively, compared with the Nehalem and  ...  The authors kindly thank Paulius Mickievicius for providing us with the optimized GPU code version and his numerous insightful comments.  ... 
doi:10.1145/2063384.2063482 dblp:conf/sc/KruegerDSMWOP11 fatcat:o2e6edp2ybcaxb6z3bs5wrovji

Design Space Exploration and Run-Time Adaptation for Multicore Resource Management Under Performance and Power Constraints [chapter]

Santiago Pagani, Muhammad Shafique, Jörg Henkel
2017 Handbook of Hardware/Software Codesign  
Secondly, it discusses the possible optimization goals and constraints of resource management techniques: computational performance, power consumption, energy consumption, and temperature.  ...  Finally, it details the state-of-the-art techniques on resource management for performance optimization under power and thermal constraints, as well as for energy optimization under performance constraints  ...  Adaptation for Multicore : : : Design Space Exploration and Run-Time Adaptation for Multicore : : : Design Space Exploration and Run-Time Adaptation for Multicore : : :  ... 
doi:10.1007/978-94-017-7267-9_11 fatcat:fogowdkcx5d6dkehsysajfa5je

Closed Loop Experiment Manager (CLEM)—An Open and Inexpensive Solution for Multichannel Electrophysiological Recordings and Closed Loop Experiments

Hananel Hazan, Noam E. Ziv
2017 Frontiers in Neuroscience  
There is growing need for multichannel electrophysiological systems that record from and interact with neuronal systems in near real-time.  ...  Finally, they should provide powerful, yet reasonably easy to implement facilities for developing closed-loop protocols for interacting with neuronal systems.  ...  AUTHOR CONTRIBUTIONS HH coded the software, analyzed its performance and wrote the manuscript. NEZ conceived the project, coded the software, and wrote the manuscript.  ... 
doi:10.3389/fnins.2017.00579 pmid:29093659 pmcid:PMC5651259 fatcat:ed5y2is3fjhcbasyij6ad5ixoy

Software-defined Radios: Architecture, State-of-the-art, and Challenges [article]

Rami Akeela, Behnam Dezfouli
2018 arXiv   pre-print
In addition, we highlight key contrasts between SDR architectures with regards to energy, computing power, and area, based on a set of metrics.  ...  Software-defined Radio (SDR) is a programmable transceiver with the capability of operating various wireless communication protocols without the need to change or update the hardware.  ...  In addition, researchers prefer GPPs since they are more familiar with them and their software frameworks, compared to DSPs and FPGAs.  ... 
arXiv:1804.06564v1 fatcat:ogkut4aibnfarbrvjkihdfiqnu

Energy Efficiency for Ultrascale Systems: Challenges and Trends from Nesus Project

2015 Supercomputing Frontiers and Innovations  
The analysis contains major areas that are related to studies of energy efficiency in ultrascale systems: heterogeneous and low power hardware architectures, power monitoring at large scale, modeling and  ...  Therefore, this paper presents challenges and trends associated with energy efficiency for ultrascale systems based on current activities of the working group on "Energy Efficiency" in the European COST  ...  That is why we developed a second scheme. The second scheme improves transfer of "short time lived" data.  ... 
doi:10.14529/jsfi150206 fatcat:uaq7p3nalvb7jb6xnholszwpla

NoC-Based Hardware Accelerator for Breakpoint Phylogeny

Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman
2012 IEEE transactions on computers  
Exponential time algorithms that apply efficient runtime heuristics, such as branch-and-bound, to dynamically prune the search space are used to solve TSP.  ...  Experimental results show that this new implementation is able to achieve speedups of up to three orders of magnitude over state-of-the-art multithreaded software implementations.  ...  This is based on a comparison of network latency and power consumption across the two frameworks.  ... 
doi:10.1109/tc.2011.100 fatcat:pvg6d4n3b5bcjgjbn6cwd4fkjy
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