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Benchmarking for large-scale placement and beyond

Saurabh N. Adya, Mehmet C. Yildiz, Igor L. Markov, Paul G. Villarrubia, Phiroze N. Parakh, Patrick H. Madden
2003 Proceedings of the 2003 international symposium on Physical design - ISPD '03  
Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results  ...  We outline major outstanding problems and discuss the future of placement benchmarking. Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.  ...  Andrew Kahng (UCSD) and Xiaojian Yang (Synplicity) for technical discussions and help with placement tools.  ... 
doi:10.1145/640020.640022 fatcat:p73s22gdpvgchgqyryfrj2bt7q

Benchmarking for Large-Scale Placement and Beyond

S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia, P.N. Parakh, P.H. Madden
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results  ...  We outline major outstanding problems and discuss the future of placement benchmarking. Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.  ...  Andrew Kahng (UCSD) and Xiaojian Yang (Synplicity) for technical discussions and help with placement tools.  ... 
doi:10.1109/tcad.2004.825852 fatcat:gu2ogxlkjjdvnd6rv7rf2ftmiq

Benchmarking for large-scale placement and beyond

Saurabh N. Adya, Mehmet C. Yildiz, Igor L. Markov, Paul G. Villarrubia, Phiroze N. Parakh, Patrick H. Madden
2003 Proceedings of the 2003 international symposium on Physical design - ISPD '03  
Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results  ...  We outline major outstanding problems and discuss the future of placement benchmarking. Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.  ...  Andrew Kahng (UCSD) and Xiaojian Yang (Synplicity) for technical discussions and help with placement tools.  ... 
doi:10.1145/640000.640022 dblp:conf/ispd/AdyaYMVPM03 fatcat:kumg4u2hpvfizii3m6fljumaa4

A Survey of Machine Learning for Computer Architecture and Systems [article]

Nan Wu, Yuan Xie
2021 arXiv   pre-print
It has been a long time that computer architecture and systems are optimized to enable efficient execution of machine learning (ML) algorithms or models.  ...  For ML-based design methodology, we follow a bottom-up path to review current work, with a scope of (micro-)architecture design (memory, branch prediction, NoC), coordination between architecture/system  ...  global ANN predicts globally optimal NoC configurations exploiting local optimal energy consumption predicted by local ANNs.  ... 
arXiv:2102.07952v1 fatcat:vzj776a6abesljetqobakoc3dq

2019 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 38

2019 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., +, TCAD Aug. 2019 1515-1528 RePlAce: Advancing Solution Quality and Routability Validation in Global Placement.  ...  ., +, TCAD Nov. 2019 1981-1994 RePlAce: Advancing Solution Quality and Routability Validation in Global Placement.  ... 
doi:10.1109/tcad.2020.2964359 fatcat:qjr6i73tkrgnrkkmtjexbxberm

Logic Synthesis [chapter]

2017 Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology  
PLACEMENT AND ROUTABILITY WITH COMPLEX DESIGN RULES Multiple patterning to fabricate smaller feature sizes has added signi cant design rule complexity that has complicated both placement and routing. e  ...  ., Closing the gap between global and detailed placement: Techniques for improving routability, Proceedings of the International Symposium on Physical Design, Monterey, CA, 2015. 51. A. Kennings, N.  ... 
doi:10.1201/9781315215112-13 fatcat:me52zpnxyfcczh3choo2p4zulm

Efficient FPGA Implementation of OpenCL High-Performance Computing Applications via High-Level Synthesis

Fahad Bin Muslim, Liang Ma, Mehdi Roozmeh, Luciano Lavagno
2017 IEEE Access  
Researchers at Baidu are thus considering FPGAs for accelerating their deep learning models for image search [8] .  ...  All these optimizations were complemented by the conventional HLS-based datapath optimization options e.g. pipelining and unrolling both the explicit and the implicit loops in the kernels (i.e. the loops  ...  Since 1993, he has been a Professor with the Politecnico di Torino, Italy. He co-authored four books and more than 200 scientific papers.  ... 
doi:10.1109/access.2017.2671881 fatcat:t2l3cjqzc5hg3a2amiff4tiek4

Survey of Methodologies, Approaches, and Challenges in Parallel Programming Using High-Performance Computing Systems

Paweł Czarnul, Jerzy Proficz, Krzysztof Drypczewski
2020 Scientific Programming  
This paper provides a review of contemporary methodologies and APIs for parallel programming, with representative technologies selected in terms of target system type (shared memory, distributed, and hybrid  ...  of parallelism, constructs enabling parallelism and synchronization, features introduced in recent versions indicating trends, support for hybridity in parallel execution, and disadvantages.  ...  OpenACC Performance Easy, similar to the OpenMP's directive-based model, however requires awareness of overheads and corresponding needs for optimization related to, e.g., data placement, copy  ... 
doi:10.1155/2020/4176794 fatcat:j52aegknyrdxzg2nopk73g3uly

QoE Management of Multimedia Streaming Services in Future Networks: A Tutorial and Survey

Alcardo Alex Barakabitze, Nabajeet Barman, Arslan Ahmad, Saman Zadtootaghaj, Lingfen Sun, Maria G. Martini, Luigi Atzori
2019 IEEE Communications Surveys and Tutorials  
We start with a high level description of QoE management for multimedia services, which integrates QoE modelling, monitoring, and optimization.  ...  issues in QoE optimization.  ...  [339] , where binocular receptive field properties are learned and aligned with human visual perception. Chen et al.  ... 
doi:10.1109/comst.2019.2958784 fatcat:7bgzl5rpmfgedo5e5psz7i3t4a

Bias Busters: Robustifying DL-based Lithographic Hotspot Detectors Against Backdooring Attacks [article]

Kang Liu, Benjamin Tan, Gaurav Rajavendra Reddy, Siddharth Garg, Yiorgos Makris, Ramesh Karri
2020 arXiv   pre-print
Deep learning (DL) offers potential improvements throughout the CAD tool-flow, one promising application being lithographic hotspot detection.  ...  Deep learning (DL) based approaches, in particular, have recently demonstrated state-ofthe-art performance in problems such as lithographic hotspot detection [1] and routability analysis [2] , and promise  ...  explicit human-driven feature engineering.  ... 
arXiv:2004.12492v1 fatcat:n244tm5tb5dspilupo7cm4kc5i

Program

2021 2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW)  
with Optimized Memory Usage Shen-Fu Hsiao (National Sun Yat-sen University, Taiwan); Jyun-Liang Chen, Yi Hsu and Xiang-Ting Huang (National Sun Yat-Sen University, Taiwan) A complete deep learning  ...  of 10 m from the goal using deep learning.  ... 
doi:10.1109/icce-tw52618.2021.9602919 fatcat:aetmvxb7hfah7iuucbamos2wgu

Coarse-Grained Reconfigurable Array Architectures [chapter]

Bjorn De Sutter, Praveen Raghavan, Andy Lambrechts
2013 Handbook of Signal Processing Systems  
So, even for tightly-coupled CGRA designs, the above loop transformations and the enabled optimizations need to be applied with great care.  ...  be opti-mized with induction variable optimizations.  ... 
doi:10.1007/978-1-4614-6859-2_18 fatcat:67as5n47rjgy7h2ouudh6pfn3e

Coarse-Grained Reconfigurable Array Architectures [chapter]

Bjorn De Sutter, Praveen Raghavan, Andy Lambrechts
2010 Handbook of Signal Processing Systems  
So, even for tightly-coupled CGRA designs, the above loop transformations and the enabled optimizations need to be applied with great care.  ...  be opti-mized with induction variable optimizations.  ... 
doi:10.1007/978-1-4419-6345-1_17 fatcat:z6ofpiaaxbffjdfpg5nac4uhbq

HRL: Efficient and flexible reconfigurable logic for near-data processing

Mingyu Gao, Christos Kozyrakis
2016 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)  
For NDP systems running MapReduce, graph processing, and deep neural networks, HRL achieves 92% of the peak performance of an NDP system based on custom accelerators for each application.  ...  Second, the packing and placement algorithms need to balance the routability and critical path latency between the two networks to achieve the overall best performance.  ...  To provide some additional placement flexibility, we use a 6 × 6 HRL array with 20 FUs, 10 OMBs, and 6 CLBs with a layout similar to Figure 3 .  ... 
doi:10.1109/hpca.2016.7446059 dblp:conf/hpca/GaoK16 fatcat:46yt3s3vznd23ma4aaszp3jfdy

Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices

Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Venkat Anantharam, Martin Wainwright
2009 IEEE Transactions on Communications  
The optimal density target depends on the tradeoff between routability and wire distance.  ...  Even with optimized floor plan and buffer placement technique, the area utilization rate is only 50%.  ... 
doi:10.1109/tcomm.2009.11.080105 fatcat:nokjs4c6rbddnp6nijzkmuhulu
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