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Fast Hardware Implementation of an Hadamard Transform Using RVC-CAL Dataflow Programming

Khaled Jerbi, Matthieu Wipliez, Mickael Raulet, Olivier Deforges, Marie Babel, Mohamed Abid
2010 2010 5th International Conference on Embedded and Multimedia Computing  
This paper presents a global design method going from high level description to implementation. The first step consists in describing an algorithm as a dataflow program with the RVC-CAL language.  ...  The final step consists in an automatic generation of an efficient hardware implementation from the dataflow program.  ...  DATAFLOW PROGRAMMING FOR HARDWARE IMPLEMENTATION The purpose of this work is to obtain a dataflow description directly from an RVC-CAL design.  ... 
doi:10.1109/emc.2010.5575731 fatcat:fl6uwhfx4fhdnpu2l6bhztgzjm

Hardware Compilation Using Attribute Grammars [chapter]

G. Economakos, G. Papakonstantinou, K. Pekmestzi, P. Tsanakas
1997 IFIP Advances in Information and Communication Technology  
In this paper, these past results are further elaborated and integrated in the construction of a prototype for an attribute granunar driven hardware compiler from behavioral descriptions to VHDL Ih!  ...  Previous work has shown that attribute grammars can be effectively adopted to hamDe high-level hardware synthesis.  ...  The first step in this methodology is the high-level synthesis of a behavioral description petformed by hardware compilation tools.  ... 
doi:10.1007/978-0-387-35190-2_18 fatcat:ahv327tqovaj7pab5zmyu3fzbq

Java as a specification language for hardware-software systems

Helaihel, Olukotun
1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97  
Our results for sample designs show that the analysis can extract fine to coarse-grained concurrency for subsequent hardware-software partitioning and co-synthesis steps of the hardware-software codesign  ...  The specification language is a critical component of the hardware-software co-design process since it is used for functional validation and as a starting point for hardwaresoftware partitioning and co-synthesis  ...  Hardware-software systems are multi-process systems, so partitioning and co-synthesis tools which map behavioral specifications to these systems need to make hardware-software trade-offs [13] .  ... 
doi:10.1109/iccad.1997.643613 dblp:conf/iccad/HelaihelO97 fatcat:z2r4ykqrlfeuho5ozvgdsmgcya

Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators

Claudio Rubattu, Francesca Palumbo, Carlo Sau, Ruben Salvador, Jocelyn Serot, Karol Desnos, Luigi Raffo, Maxime Pelcat
2019 IEEE Embedded Systems Letters  
Unfortunately, system specialization is by nature a nightmare from the design productivity perspective.  ...  Domain-specific acceleration is now a "must" for all the computing spectrum, going from high performance computing to embedded systems.  ...  DFN specifications; 2) a dataflow-to-hardware mapper, the Platform Composer (PC), deploys an HDL description of the CGR datapath.  ... 
doi:10.1109/les.2018.2882989 fatcat:uh7mhmyw4bh4xciykwb6bnepgy

Design of Embedded Systems: Formal Models, Validation, and Synthesis [chapter]

Stephen Edwards, Luciano Lavagno, Edward A. Lee, Alberto Sangiovanni-Vincentelli
2002 Readings in Hardware/Software Co-Design  
The concurrent design process for such embedded systems involves solving the specification, validation, and synthesis problems.  ...  Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software.  ...  Lavagno and Sangiovanni-Vincentelli were partially supported by grants from Cadence, Magneti Marelli, Daimler-Benz, Hitachi, Consiglio Nazionale delle Ricerche, the MICRO program, and SRC.  ... 
doi:10.1016/b978-155860702-6/50009-0 fatcat:um7k7am5ergnrcizrrkbmzoz7a

Design of embedded systems: formal models, validation, and synthesis

S. Edwards, L. Lavagno, E.A. Lee, A. Sangiovanni-Vincentelli
1997 Proceedings of the IEEE  
The concurrent design process for such embedded systems involves solving the specification, validation, and synthesis problems.  ...  Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software.  ...  Lavagno and Sangiovanni-Vincentelli were partially supported by grants from Cadence, Magneti Marelli, Daimler-Benz, Hitachi, Consiglio Nazionale delle Ricerche, the MICRO program, and SRC.  ... 
doi:10.1109/5.558710 fatcat:4v34mhx7hjf5zjt4aap356zvb4

Codesign of embedded systems: status and trends

R. Ernst
1998 IEEE Design & Test of Computers  
Notably, out of these global policies, only the static uniform approach supports global buffering between components, which is explained by the complex behavior of preemptive scheduling.  ...  On the hardware side, we see a growing set of high-level synthesis tools: the Behavioral Compiler of Synopsys, Monet of Menor Graphics, and RapidPath of DASYS.  ... 
doi:10.1109/54.679207 fatcat:7ghyeusfczbepg5adsbge3qvhu

Reconfigurable video coding

Jörn W. Janneck, Marco Mattavelli, Mickael Raulet, Matthieu Wipliez
2010 Proceedings of the first annual ACM SIGMM conference on Multimedia systems - MMSys '10  
This paper presents the RVC framework and its underlying dataflow programming model, along with the tool support and initial results.  ...  The former leads to unnecessary complexity in the standardization process, while the latter implies that implementations have to be rebuilt from the ground up to reflect the parallel nature of the target  ...  The hardware code generator presented in more details in [15] is part of Orcc, it generates a hardware description from Cal by translating Orcc's intermediate representation to a lower-level IR called  ... 
doi:10.1145/1730836.1730864 dblp:conf/mmsys/JanneckMRW10 fatcat:5stvtb4ghfgtnezviir4qgffl4

High-Level Synthesis: Past, Present, and Future

G. Martin, G. Smith
2009 IEEE Design & Test of Computers  
The second generation was the first age of commercial EDA, behavioral-synthesis tools driven by hardware description languagesÀ Àand it was a commercial failure.  ...  At a time when most design teams were just moving from schematic capture to standard hardware description languages (HDLs) at the RTL, adopting new and obscure input languages such as Silage for a new  ... 
doi:10.1109/mdt.2009.83 fatcat:yimb2nmhrzgbhnaw2nluqewnea

Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case study

Jorn W. Janneck, Ian D. Miller, David B. Parlour, Ghislain Roquier, Matthieu Wipliez, Mickael Raulet
2008 2008 IEEE Workshop on Signal Processing Systems  
CAL data flow models expose the intrinsic concurrency of the algorithms by employing the notions of actor programming and dataflow.  ...  This paper described in details the principles on which such code generators are based and shows how efficient software (C) and hardware (VHDL and Verilog) code can be generated by appropriate CAL models  ...  HARDWARE SYNTHESIS FROM CAL DATAFLOW MODELS Fig. 6. Hardware synthesis results for an MPEG-4 Simple Profile decoder. The numbers are compared with a reference hand written design in VHDL.  ... 
doi:10.1109/sips.2008.4671777 dblp:conf/sips/JanneckMPRWR08 fatcat:ev5nhvqmunauzhjveqbzke2ehq

Efficient System-Level Hardware Synthesis of Dataflow Programs Using Shared Memory Based FIFO

Mariem Abid, Khaled Jerbi, Mickaël Raulet, Olivier Déforges, Mohamed Abid
2017 Journal of Signal Processing Systems  
The design flow combines a dataflow compiler for generating C-based HLS descriptions from a dataflow description and a C-to-gate synthesizer for generating Register-Transfer Level (RTL) descriptions.  ...  These results were demonstrated upon the hardware synthesis of the emerging High-Efficiency Video Coding (HEVC) standard.  ...  Design synthesis is a path through the Gajski-Kuhn Ychart from a high-level (of abstraction) behavioral domain description to a low-level physical domain description.  ... 
doi:10.1007/s11265-017-1226-x fatcat:ewevwhnbibao5hsh26fgjl2tga

Hierarchical Dataflow Model for efficient programming of clustered manycore processors

Julien Hascoet, Karol Desnos, Jean-Francois Nezan, Benoit Dupont de Dinechin
2017 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP)  
This paper introduces a technique for deploying hierarchical dataflow graphs efficiently onto MPSoC.  ...  The proposed technique exploits different granularity of dataflow parallelism to generate both NoC-based communications and nested OpenMP loops.  ...  The process responsible for generating efficient multi-core code from a portable dataflow description, for a specified target architecture, is called software synthesis [2] .  ... 
doi:10.1109/asap.2017.7995270 dblp:conf/asap/HascoetDND17 fatcat:zrl6ffctonhrzixhzhh35nbzdy

Spatial computation

Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein
2004 ACM SIGOPS Operating Systems Review  
As a consequence, ASH hardware is fast and extremely power efficient.  ...  work we demonstrate three features of ASH: (1) that such architectures can be built by automatic compilation of C programs; (2) that distributed computation is in some respects fundamentally different from  ...  High-level synthesis. While there is a substantial amount of research on hardware synthesis from high-level languages, and dialects of C and C++, none of it supports C as fully as CASH does.  ... 
doi:10.1145/1037949.1024396 fatcat:gycsxj3ebfhazpstc2dbx6ebiq

Spatial computation

Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein
2004 SIGARCH Computer Architecture News  
As a consequence, ASH hardware is fast and extremely power efficient.  ...  work we demonstrate three features of ASH: (1) that such architectures can be built by automatic compilation of C programs; (2) that distributed computation is in some respects fundamentally different from  ...  High-level synthesis. While there is a substantial amount of research on hardware synthesis from high-level languages, and dialects of C and C++, none of it supports C as fully as CASH does.  ... 
doi:10.1145/1037947.1024396 fatcat:5jkfjbhrdzamrdmhosahxd6dzu

Spatial computation

Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein
2004 SIGPLAN notices  
As a consequence, ASH hardware is fast and extremely power efficient.  ...  work we demonstrate three features of ASH: (1) that such architectures can be built by automatic compilation of C programs; (2) that distributed computation is in some respects fundamentally different from  ...  High-level synthesis. While there is a substantial amount of research on hardware synthesis from high-level languages, and dialects of C and C++, none of it supports C as fully as CASH does.  ... 
doi:10.1145/1037187.1024396 fatcat:5jeulzqygbfnnkch33wohm3imi
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