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Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units

Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
2011 IPSJ Transactions on System LSI Design Methodology  
In this paper, we present a prototype MIPS R3000 processor, which integrates the fine-grained power gating technique into its functional units.  ...  The prototype chip -Geyser-1 has been implemented with Fujitsu's 65 nm CMOS technology; and to facilitate the design process with fine-grained power gating, a fully automated design flow has also been  ...  Conclusion and Future Work Geyser-1, a prototype MIPS R3000 processor which implements the finegrained power gating control on its functional units, has been presented.  ... 
doi:10.2197/ipsjtsldm.4.182 fatcat:otquktpinzga3erietntkbime4

Normally-off computing project: Challenges and opportunities

Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa
2014 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)  
gets active when an affecting instruction enters the IF stage  The activated EX-unit returns to sleep mode after execution Prototype CPU : Geyser-1MIPS R3000  Fujitsu e-shuttle 65nm  ...  Sends wake-up signal Operation  MIPS compatible processor with 5-stage pipeline  Straightforward Fine Grain Run Time Power Gating  Turn EX-units into active mode only if necessary  Ex-unit  ... 
doi:10.1109/aspdac.2014.6742850 dblp:conf/aspdac/NakamuraNM14 fatcat:sekbtoqbtjh6hmyz6glwwiyclu

A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA

Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano
2015 International Journal of Networking and Computing  
Cool Mega Array (CMA) is an energy efficient reconfigurable accelerator consisting of a large PE array with combinatorial circuits and a small microcontroller.  ...  By partly replacing the programmable microcontroller by the host processor Geyser with a dedicated hardware controller, the setting up for the CMA and data transfer can be efficiently done.  ...  This work is also supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc.  ... 
doi:10.15803/ijnc.5.1_239 fatcat:7uyi7qat45epdat4d3utzv7ty4

A Co-processor Design of an Energy Efficient Reconfigurable Accelerator CMA

Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano
2013 2013 First International Symposium on Computing and Networking  
Cool Mega Array (CMA) is an energy efficient reconfigurable accelerator consisting of a large PE array with combinatorial circuits and a small microcontroller.  ...  By partly replacing the programmable microcontroller by the host processor Geyser with a dedicated hardware controller, the setting up for the CMA and data transfer can be efficiently done.  ...  This work is also supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc.  ... 
doi:10.1109/candar.2013.28 dblp:conf/ic-nc/IzawaOKUA13 fatcat:mfgv4pdgtbgzfo2jm6xhh4llba