Filters








705 Hits in 6.8 sec

Geometric Approach for Optimal Routing on a Mesh with Buses

Yosi Ben-Asher, Ilan Newman
1997 Journal of computer and system sciences (Print)  
We consider 1 1 routing of m packets in a d-dimensional mesh with n d processors and d } n d&1 buses (one per row and column).  ...  The architecture of"mesh of buses" is an important model in parallel computing.  ...  For CREW, routing on meshes with buses can be done faster than routing without buses, and faster still using buses combined with point-to-point communication.  ... 
doi:10.1006/jcss.1997.1492 fatcat:7ccdpjaw2rfaffdz2dx6plw2rq

Page 2550 of Mathematical Reviews Vol. , Issue 98D [page]

1998 Mathematical Reviews  
98d:68024 98d:68024 68M10 68Q10 Ben-Asher, Yosi (IL-HAIF; Haifa); Newman, Ilan (IL-HAIF; Haifa) Geometric approach for optimal routing on a mesh with buses. (English summary) J. Comput.  ...  We con- sider 1-1 routing of m packets in a d-dimensional mesh with n4 processors and d -n4~' buses (one per row and column).  ... 

Bristle blocks: a silicon compiler

D. Johannsen
1988 Papers on Twenty-five years of electronic design automation - 25 years of DAC  
This Lype of file sysLem usually does noL aid in the acLUa/ computation of silicon layouL. and can hinder a designer with program constraints that have lillie or nothing to do with silicon constraints.  ...  The Bristle Block system is an auempt Lo create a silicon compiler that will perfonn the majority of the implementation computation while placing a minimum set of conslraints on the designer.  ...  Along with meshing of cells, the busing requirements between cells must also be met. Buses may need to break or stop, and bus prechargc circuits must be added for each bus.  ... 
doi:10.1145/62882.62903 fatcat:g42le2aidbbaznm2yhaj7hnr5q

Bristle Blocks: A Silicon Compiler

D. Johannsen
1979 16th Design Automation Conference  
This Lype of file sysLem usually does noL aid in the acLUa/ computation of silicon layouL. and can hinder a designer with program constraints that have lillie or nothing to do with silicon constraints.  ...  The Bristle Block system is an auempt Lo create a silicon compiler that will perfonn the majority of the implementation computation while placing a minimum set of conslraints on the designer.  ...  Along with meshing of cells, the busing requirements between cells must also be met. Buses may need to break or stop, and bus prechargc circuits must be added for each bus.  ... 
doi:10.1109/dac.1979.1600125 fatcat:tic5eztghba2bgy5ohzdznbhju

Timely data delivery in a realistic bus network

Utku Acer, Paolo Giaccone, David Hay, Giovanni Neglia, Saed Tarapiah
2011 2011 Proceedings IEEE INFOCOM  
Through an extensive simulation study, we compare the optimal routing algorithm with three other approaches: minimizing the expected traversal time over our graph, maximizing the delivery probability over  ...  This paper studies the routing problem in such a network. Assuming the bus schedule is known, we maximize the delivery probability by a given deadline for each packet.  ...  Rafael Aguilar from 5T (Tecnologie Telematiche Trasporti Traffico Torino) for the traces they provided us and for their availability to explain and discuss the details of Turin public transportation system  ... 
doi:10.1109/infcom.2011.5935201 dblp:conf/infocom/AcerGHNT11 fatcat:zqo6dl4b4jdebfa5snkrroxgha

Timely Data Delivery in a Realistic Bus Network

U. G. Acer, P. Giaccone, D. Hay, G. Neglia, S. Tarapiah
2012 IEEE Transactions on Vehicular Technology  
Through an extensive simulation study, we compare the optimal routing algorithm with three other approaches: minimizing the expected traversal time over our graph, maximizing the delivery probability over  ...  This paper studies the routing problem in such a network. Assuming the bus schedule is known, we maximize the delivery probability by a given deadline for each packet.  ...  Rafael Aguilar from 5T (Tecnologie Telematiche Trasporti Traffico Torino) for the traces they provided us and for their availability to explain and discuss the details of Turin public transportation system  ... 
doi:10.1109/tvt.2011.2179072 fatcat:3doyyfo4trbntdcnwyxdkasphe

Early wire characterization for predictable network-on-chip global interconnects

Ilhan Hatirnaz, Stephane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De-Micheli
2007 Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07  
with respect to existing techniques.  ...  This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design.  ...  This approach enables a faster convergence for more optimal solutions compared to the ones provided by standard techniques.  ... 
doi:10.1145/1231956.1231969 dblp:conf/slip/HatirnazBPLMAM07 fatcat:t6v6g2qnk5be3i3ywm3uwxpwdm

A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture

Zhibin Xiao, Bevan Baas
2012 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)  
2-Dimensional meshes are the most commonly used Network-on-Chip (NoC) topology for on-chip communication in many-core processor arrays due to their low complexity and excellent match to rectangular processor  ...  However, 2D meshes may incur local traffic congestion for applications with significant levels of traffic with non-neighboring cores, resulting in long latencies and high power consumption.  ...  RELATED WORK Many topologies have been used for on-chip inter-processor communication, such as buses, meshes, tori, binary trees, octagons, hierarchical buses and custom topologies for specific applications  ... 
doi:10.1109/vlsi-soc.2012.6379022 dblp:conf/vlsi/XiaoB12 fatcat:2dp4q5igs5cn5lj5rt6m2opcxe

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks [chapter]

Zhibin Xiao, Bevan Baas
2013 IFIP Advances in Information and Communication Technology  
The authors thank Dean Truong for the offset-row topology idea as well as the chip layout assistance, Anh Tran for providing the 2D mesh mapping of the 802.11a WLAN baseband receiver, P.  ...  acknowledge support from ST Microelectronics, Intel, UC Micro, NSF Grant 0430090 and CAREER Award 0546907, SRC GRC Grant 1598, CSR Grant 1659, Intellasys, S Machines and the support of the C2S2 Focus Center, one  ...  Related Work Many topologies have been used for on-chip inter-processor communication, such as buses, meshes, tori, binary trees, octagons, hierarchical buses and custom topologies for specific applications  ... 
doi:10.1007/978-3-642-45073-0_7 fatcat:g2wcu2i6qzcypfk4skmyqylqma

Multi-Parametric Investigations on Aerodynamic Force, Aeroacoustic, and Engine Energy Utilizations Based Development of Intercity Bus Associates with Various Drag Reduction Techniques through Advanced Engineering Approaches

Yinyin Wang, Vijayanandh Raja, Senthil Kumar Madasamy, Sujithira Padmanaban, Hussein A. Z. AL-bonsrulah, Manivel Ramaiah, Parvathy Rajendran, Arul Prakash Raji, Anselme Muzirafuti, Fuzhang Wang
2022 Sustainability  
Last, for real-time applications, multi-parametric studies based on appropriate intercity buses are established.  ...  As a result, much study is required to determine how opposing aerodynamic forces and side drifting force affects function, as well as how to deal with them for safe and smooth navigation.  ...  all other mesh instances; hence, case 3 mesh approaches were chosen for all further analyses.  ... 
doi:10.3390/su14105948 fatcat:vkbdxlo7ezcvliu2jknxjf2lti

Enhancing effective throughput for transmission line-based bus

Aaron Carpenter, Jianyun Hu, Ovunc Kocabas, Michael Huang, Hui Wu
2012 SIGARCH Computer Architecture News  
We find transmission line-based buses to be a more compelling interconnect even for large-scale chipmultiprocessors, and thus bring into doubt the centrality of packet switching in future on-chip interconnect  ...  network-on-chip (NoC) architecture.  ...  For brevity, we only show the (geometric) mean and the range of relative performance.  ... 
doi:10.1145/2366231.2337178 fatcat:yhxf6dtu2zfw7p44lwjw4u2a6i

Enhancing effective throughput for transmission line-based bus

Aaron Carpenter, Jianyun Hu, Ovunc Kocabas, Michael Huang, Hui Wu
2012 2012 39th Annual International Symposium on Computer Architecture (ISCA)  
We find transmission line-based buses to be a more compelling interconnect even for large-scale chipmultiprocessors, and thus bring into doubt the centrality of packet switching in future on-chip interconnect  ...  network-on-chip (NoC) architecture.  ...  For brevity, we only show the (geometric) mean and the range of relative performance.  ... 
doi:10.1109/isca.2012.6237015 dblp:conf/isca/CarpenterHKHW12 fatcat:u3v7nq6qf5c7hi7b4brvi6aidi

Bio-inspired thermal management techniques for three dimensional heterogeneous stacked network-on-chip systems

Ranjita Kumari Dash, Jose L. Risco-Martin, Ashok Kumar Turuk, Jose L. Ayala
2016 2016 International Conference on Bio-engineering for Smart Technologies (BioSMART)  
architecture with 3 layers is used as the baseline for our experimental work.  ...  As our approach is independent of any topology, it paves the way for thermal driven design methods consisting of 3D layouts made up of several layers.  ...  The inter-layer communication is carried out with a set of buses that route the communication signals from one layer to another.  ... 
doi:10.1109/biosmart.2016.7835601 fatcat:pr32cgqxsretzgw7ogbenjbsxa

Bus Service Level and Horizontal Equity Analysis in the Context of the Modifiable Areal Unit Problem

Maurici Ruiz-Pérez, Joana Maria Seguí-Pons
2021 ISPRS International Journal of Geo-Information  
The results show significant variations of the optimal frequencies obtained, depending on the type of zoning used.  ...  m mesh.  ...  This provided a service level value for each geographical unit, based on the number of buses passing through bus stops within 400 m.  ... 
doi:10.3390/ijgi10030111 fatcat:q63ic4daijb2degoqdptvttd4e

Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links

Sebastian Werner, Javier Navaridas, Mikel Lujan
2017 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)  
Moreover, when optimally combined with electrical links for short distances, this can be done without trading off latency.  ...  We present the effectiveness of this concept with Lego, our hybrid, mesh-based NoC that provides high power efficiency by utilizing electrical links for local traffic, and low-bandwidth optical links for  ...  Based on our routing algorithm, incoming data on the mesh links is always intended for the local core. Therefore, no routing computation has to be performed.  ... 
doi:10.1109/hpca.2017.23 dblp:conf/hpca/WernerNL17 fatcat:cicpbworurbxrhor6kja5on7v4
« Previous Showing results 1 — 15 out of 705 results