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Generic global placement and floorplanning

Hans Eisenmann, Frank M. Johannes
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
Our algorithm is capable of addressing the problems of global placement, floorplanning, timing minimization and interaction to logic synthesis.  ...  We present a new force directed method for global placement. Besides the well-known wire length dependent forces we use additional forces to reduce cell overlaps and to consider the placement area.  ...  Section 5 illustrates applications for generic cell placement, floorplanning, timing minimization and interaction with logic synthesis.  ... 
doi:10.1145/277044.277119 dblp:conf/dac/EisenmannJ98 fatcat:ianedaiwwjhc7om25olq2wg6wy

Generic global placement and floorplanning

H. Eisenmann, F.M. Johannes
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)  
Our algorithm is capable of addressing the problems of global placement, floorplanning, timing minimization and interaction to logic synthesis.  ...  We present a new force directed method for global placement. Besides the well-known wire length dependent forces we use additional forces to reduce cell overlaps and to consider the placement area.  ...  Section 5 illustrates applications for generic cell placement, floorplanning, timing minimization and interaction with logic synthesis.  ... 
doi:10.1109/dac.1998.724480 fatcat:72an33n6svdpxh6qn3zvbhv7iy

Book announcement

1992 Discrete Applied Mathematics  
Placement improvement and placement heuristics). General cells: Floorplanning (Floorplanning based on mincut (Floorplanning based on oriented mincut (Similarity relation for oriented mincut.  ...  Layout strategies and styles (Placement and routing of general cells. Standard cells. Gate arrays. Sea of gates. Printed circuit boards. Floorplanning)). Summary. Chapter 2: Optimizufion Problems.  ... 
doi:10.1016/0166-218x(92)90299-p fatcat:kkkpojidyvgifm6vpfwb5c2epi

Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model [article]

Bapi Kar, Susmita Sur-Kolay, Chittaranjan Mandal
2018 arXiv   pre-print
This paper presents a generalized model for early global routability assessment, HGR, by utilizing the free regions over the blocks beyond certain metal layers.  ...  This starts with placement optimization aimed at improving routability, wirelength, congestion and timing in the design.  ...  Based on the results from the industrial case study, we plan for a new placement and routing framework guided by this generic early global routing method for a given floorplan solution and subsequently  ... 
arXiv:1810.12789v1 fatcat:mtm4tl7aerew5pe64bpu5ws3a4

A DSM design flow

Amir H. Salek, Jinan Lou, Massoud Pedram
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
repeated application of simultaneous floorplanning, technology mapping and gate placement along the timing critical paths.  ...  This paper presents an integrated design flow which combines floorplanning, technology mapping, and placement using a dynamic programming algorithm.  ...  •A new global area optimizer, *SiMPA-E, which optimizes chip area via simultaneous floorplanning, technology mapping, and gate placement.  ... 
doi:10.1145/277044.277072 dblp:conf/dac/SalekLP98 fatcat:smgvu7rxkjf75amulbiqwhflre

An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs

Jackey Z. Yan, Natarajan Viswanathan, Chris Chu
2014 ACM Transactions on Design Automation of Electronic Systems  
The basic idea is to use floorplanning to guide the placement of objects at the global level.  ...  There are several advantages to handling placement at the global level with a floorplanning technique. First, the problem size can be significantly reduced.  ...  Tung-Chieh Chen and Dr. Peter Spindler for the help with hMetis 2.0, ISPD05/06 placement benchmarks, mPL6, NTU-place3 and Kraftwerk, respectively. Also thanks goes to Dr. Yi-Lin Chuang and Prof.  ... 
doi:10.1145/2611761 fatcat:yues7qpdfvew5fjyxl2lbvwcm4

A pseudo-hierarchical methodology for high performance microprocessor design

A. Bertolet, G. Rodgers, D. Willmott, T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. A. Scott, R. Weiss, K. Carpenter, K. Carrig (+6 others)
1997 Proceedings of the 1997 international symposium on Physical design - ISPD '97  
Critical aspects of the methodology include an integrated database for design control, algorithmic power grid generation, fully customized clock network insertion, timing driven placement and routing,  ...  an integrated timing closure strategy, and incremental checking that includes formal netlist verification, DRC and LVS.  ...  would like to recognize the efforts of Dave Hathaway, Pete Osler, Betty Bouldin, Tad Wilder, John Doyle, Bruce Winter, Andrew Tickle, Gilles Lamant, Marc Bevis, Andrew Davis, Damian Artt, Don Perley, and  ... 
doi:10.1145/267665.267702 dblp:conf/ispd/BertoletCCCDFKPPRWBDGLMSW97 fatcat:tyvdnud24fbxvohuufqn2o5tgm

Min-cut floorplacement

J.A. Roy, S.N. Adya, D.A. Papa, I.L. Markov
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We propose to integrate min-cut placement with fixed-outline floorplanning to solve the more general placement problem, which includes cell placement, floorplanning, mixed-size placement and achieving  ...  Large macros can be handled by traditional floorplanning, but are harder to account for in min-cut and analytical placement.  ...  Below we extend our global free-shape floorplanner to generate both locations and shapes of soft modules so as to minimize interconnect.  ... 
doi:10.1109/tcad.2005.855969 fatcat:htoqbftopbd4becdgv45h3qvdq

Advances and Challenges in 3D Physical Design

Jason Cong, Guojie Luo
2010 IPSJ Transactions on System LSI Design Methodology  
This paper discusses the recent progress made on the major steps in 3D physical design, including 3D floorplanning, 3D placement, 3D routing and thermal through-silicon via (TS via) planning, and outlines  ...  Advances and Challenges in 3D Physical Design Jason Cong †1, †2 and Guojie Luo †1 The task of 3D physical design is to map a circuit from a netlist (structural) representation into a geometric (physical  ...  Acknowledgments This study is supported by the National Science Foundation (NSF) under CCF-0430077 and CCF-0528583.  ... 
doi:10.2197/ipsjtsldm.3.2 fatcat:vqsohxmfj5d4vf4zmv2ep4it6y

BlackBox Model Based VLSI Hierarchical Floorplanning

2019 International Journal of Engineering and Advanced Technology  
In the top-level chip planning the quality of the floorplanning depends on the proper alignment of blocks and easy to meet the timing and congestion.  ...  If floorplanning is not good the entire design will take more time and it will increase a greater number of iterations to complete the design.  ...  Generally, the top-level VLSI chip planning is done by using different prototypes, for each prototype estimate congestion and timing constraints based on quick placement and global routing.  ... 
doi:10.35940/ijeat.f8754.088619 fatcat:vf2howc54befpa2gi5ebu3ama4

Frontier: A Fast Placement System for FPGAS [chapter]

Russell Tessier
2000 IFIP Advances in Information and Communication Technology  
It is shown that floorplanning, routability evaluation, and back-end optimization are all necessary to achieve efficient placement solutions.  ...  Finally, if the floorplan is determined to be unroutable, a feedback-driven placement perturbation step is employed to achieve a lower cost placement.  ...  Due to macro-block shape considerations and specific interconnection patterns of individual designs, a successful floorplanning step provides no guarantee that a placement possessing close to the global  ... 
doi:10.1007/978-0-387-35498-9_12 fatcat:wpq57c5itfalzotsvstr5476s4

Improved Harmony Search Algorithm for Nonslicing Floor Planning of VLSI Chip with Fixed-Outline Constraint
ENGLISH

K.Raveendra, A V Kiranmai
2012 International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering  
Initially B*-tree is used to generate the primary floorplan for the given rectangular hard modules and HIS algorithm is applied to obtain an optimal solution for the efficient floorplan.  ...  It is used to estimate the chip area and wire length prior to the real placement of digital blocks and their interconnections.  ...  They are sequence pair [1] , bounded slicing grid [2] , O-tree [3] and B*-tree [4] representations. In general, nonslicing floorplan methods give optimal layout than the slicing floorplan.  ... 
doi:10.15662/ijareeie.2012.0104018 fatcat:z4gfg66735ck3oohettjaaawtq

Timing closure based on physical hierarchy

Jason Cong
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
over global interconnects, and extension of existing synthesis operations.  ...  First, we shall motivate our approach by pointing out the limitations of the existing approach to interconnect planning based on early RTL floorplanning following logic hierarchy.  ...  pipelining over global interconnects during physical hierarchy generation, and development of placement-aware synthesis and optimization operations.  ... 
doi:10.1145/505388.505429 dblp:conf/ispd/Cong02 fatcat:bhbrefxfrbdgnnwkzppee7gh5q

Timing closure based on physical hierarchy

Jason Cong
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
over global interconnects, and extension of existing synthesis operations.  ...  First, we shall motivate our approach by pointing out the limitations of the existing approach to interconnect planning based on early RTL floorplanning following logic hierarchy.  ...  pipelining over global interconnects during physical hierarchy generation, and development of placement-aware synthesis and optimization operations.  ... 
doi:10.1145/505428.505429 fatcat:w6kecpueabelrgsuknlypqfjhy

Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary

Leena Jain, Amarbir Singh
2013 International Journal of Computer Applications  
This survey paper gives an up-to-date account on various nonslicing floorplan representations in VLSI floorplanning. General Terms VLSI floorplanning, non-slicing floorplan, slicing floorplan.  ...  Floorplan representation is a fundamental issue in designing a VLSI floorplanning algorithm as the representation has a great impact on the feasibility and complexity of floorplan designs.  ...  All these properties make TCG an effective and flexible representation for handling the general floorplan/placement design problems with various constraints.  ... 
doi:10.5120/12433-8962 fatcat:wz6dfvhazrfdhepa44m7tbyb6u
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