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PHAST: Hardware-Accelerated Shortest Path Trees

Daniel Delling, Andrew V. Goldberg, Andreas Nowatzyk, Renato F. Werneck
2011 2011 IEEE International Parallel & Distributed Processing Symposium  
We present a novel algorithm to solve the non-negative single-source shortest path problem on road networks and graphs with low highway dimension.  ...  This makes applications based on all-pairs shortest-paths practical for continental-sized road networks.  ...  We also thank the anonymous referees for their helpful suggestions.  ... 
doi:10.1109/ipdps.2011.89 dblp:conf/ipps/DellingGNW11 fatcat:63iaqz3ulzalza2m42nuct27me

PHAST: Hardware-accelerated shortest path trees

Daniel Delling, Andrew V. Goldberg, Andreas Nowatzyk, Renato F. Werneck
2013 Journal of Parallel and Distributed Computing  
We present a novel algorithm to solve the non-negative single-source shortest path problem on road networks and graphs with low highway dimension.  ...  This makes applications based on all-pairs shortest-paths practical for continental-sized road networks.  ...  We also thank the anonymous referees for their helpful suggestions.  ... 
doi:10.1016/j.jpdc.2012.02.007 fatcat:f5ihav32nba2roejckvno3ivn4

Accelerating the Understanding of Life's Code Through Better Algorithms and Hardware Design [article]

Mohammed H K Alser
2019 arXiv   pre-print
Calculating the similarities between a pair of genomic sequences is one of the most fundamental computational steps in genomic analysis.  ...  We also demonstrate that integrating our hardware pre-alignment filters with the state-of-the-art read aligners reduces the aligner's execution time by up to 21.5x.  ...  Achieving an efficient hardware architecture raises the following question: Can one solve many small sub-problems of the Sneaky Snake Problem with a high parallelism by reducing the search space of the  ... 
arXiv:1910.03936v1 fatcat:f2sw22g2sndc5b3jasnaoizw7i

Design of Embedded Systems: Formal Models, Validation, and Synthesis [chapter]

Stephen Edwards, Luciano Lavagno, Edward A. Lee, Alberto Sangiovanni-Vincentelli
2002 Readings in Hardware/Software Co-Design  
Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software.  ...  We review the variety of approaches to these problems that have been taken.  ...  ACKNOWLEDGEMENTS Edwards and Lee participated in this study as part of the Ptolemy project, which is supported by the Advanced Research Projects Agency and the U.S.  ... 
doi:10.1016/b978-155860702-6/50009-0 fatcat:um7k7am5ergnrcizrrkbmzoz7a

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Prateek Shantharama, Akhilesh S. Thyagaturu, Martin Reisslein
2020 IEEE Access  
The hardware acceleration section in [86] focuses mainly on a tutorial introduction to the general concept of hardware offloading, mainly covering the general concepts of offloading to commodity NICs  ...  Their study considers the Quick Path Interconnect (QPI) as FPGA-to-core communication path in case of FPGA presence on the processor die (coherent shared memory between CPU and FPGA) and the PCIe interface  ... 
doi:10.1109/access.2020.3008250 fatcat:kv4znpypqbatfk2m3lpzvzb2nu

The MapReduce-based approach to improve the shortest path computation in large-scale road networks: the case of A* algorithm

Wilfried Yves Hamilton Adoni, Tarik Nahhal, Brahim Aghezzaf, Abdeltif Elbyed
2018 Journal of Big Data  
It requires exponential time computation and very costly hardware to compute the shortest path on large-scale networks.  ...  The basic algorithms used for the Single Source Shortest Path Problem (SSSPP) are not suited for intensive computation in large-scale networks because of long latency time.  ...  Competing interests The authors declare that they have no competing interests. Availability of data and materials All supporting data files are open source.  ... 
doi:10.1186/s40537-018-0125-8 fatcat:27xowjeminf27lrl43r7mexr54

GPU computing in discrete optimization. Part II: Survey focused on routing problems

Christian Schulz, Geir Hasle, André R. Brodtkorb, Trond R. Hagen
2013 EURO Journal on Transportation and Logistics  
Part II gives a broad survey of the literature on parallel computing in discrete optimization targeted at modern PCs, with special focus on routing problems.  ...  Modern commodity PCs include a multi-core CPU and at least one GPU, providing a low cost, easily accessible heterogeneous environment for high performance computing.  ...  Acknowledgements The work presented in this paper has been partially funded by the Research Council of Norway as a part of the Collab project (contract number 192905/I40, SMARTRANS), the DOMinant II project  ... 
doi:10.1007/s13676-013-0026-0 fatcat:zfalygsovfh5jauczny7wp2sga

Capacity metric for chip heterogeneous multiprocessors

Mwaffaq Otoom, JoAnn M. Paul
2011 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '11  
Performance metrics are required in order to evaluate any system, including computer systems. A lack of appropriate  ...  The primary contribution of this thesis is the development of a new performance metric, Capacity, which evaluates the performance of Chip Heterogeneous Multiprocessors (CHMs) that process multiple heterogeneous  ...  , digital signal processors, graphics processors, and/or multimedia processors, along with programmable hardware accelerators, fixed-function hardware, on-chip memory, high-speed interconnect networks,  ... 
doi:10.1145/2039370.2039404 dblp:conf/codes/OtoomP11 fatcat:gw47vtkqcvea3b32o4egauarcq

Harvesting the Aggregate Computing Power of Commodity Computers for Supercomputing Applications

Dereje Regassa, Heonyoung Yeom, Yongseok Son
2022 Applied Sciences  
Most of the parallel computing researchers focused on harnessing the power of commodity processors and even internet computers to aggregate their computation powers to solve computationally complex problems  ...  with a speedup of 1.79 and 2.47 respectively on the HPDA cluster.  ...  The comparative studies have been conducted for two problem sets the all-pairs-shortest-path problem and a joining problem for large data sets.  ... 
doi:10.3390/app12105113 fatcat:42km36vbeve23plh5e4seiw2tq

Customized architectures for faster route finding in GPS-based navigation systems

Jason Loew, Dmitry Ponomarev, Patrick H. Madden
2010 2010 IEEE 8th Symposium on Application Specific Processors (SASP)  
A key element of any navigation system is fast and effective route finding, and this depends heavily on Dijkstra's shortest path algorithm.  ...  We obtain a substantial speedup on real-world graphs (in particular, road maps), allowing the development of navigation systems that are more responsive, and also lower in total power consumption.  ...  We wish to highlight that the shortest path problem is in fact a hard serial bottleneck; while this problem has been studied in detail, no efficient and effective parallel approach has been proposed until  ... 
doi:10.1109/sasp.2010.5521148 dblp:conf/sasp/LoewPM10 fatcat:tnsiaalz25bezbh77ekn2wkyta

U2STRA

Jianting Zhang, Simin You, Le Gruenwald
2012 Proceedings of the 2012 ACM workshop on City data management workshop - CDMW '12  
In this study, we propose to develop the U 2 STRA prototype system to efficiently manage large-scale GPS trajectory data using General Purpose computing on Graphics Processing Units (GPGPU) technologies  ...  Our experiments on two publically available large trajectory datasets (GeoLife and T-Drive) have demonstrated the efficiency of massively data parallel GPGPU computing.  ...  we further perform pair-wised distance computation and find the shortest distance to S 2j for all points in S 1i .  ... 
doi:10.1145/2390226.2390229 fatcat:7v2spz6lazdgpbcbynxpvxu6xe

A multilayer solution for path provisioning in new-generation optical/MPLS networks

R. Sabella, M. Settembre, G. Oriolo, F. Razza, F. Ferlito, G. Conte
2003 Journal of Lightwave Technology  
As a solution, we propose a new heuristic algorithm based on the shortest path computation and a mathematical programming approach, which makes use of the optimization solver CPLEX.  ...  A large computational study shows the effectiveness of the former, in terms of quality of the solutions.  ...  ACKNOWLEDGMENT The authors wish to sincerely thank Dr. S. Canale and Dr. A. Pacifici for fruitful discussions.  ... 
doi:10.1109/jlt.2003.811424 fatcat:uilesch5rncaji22jt3vnjxsie

Simian integrated framework for parallel discrete event simulation on GPUS

Guillaume Chapuis, Stephan Eidenbenz, Nandakishore Santhi, Eun Jung Park
2015 2015 Winter Simulation Conference (WSC)  
Recently, Graphics Processing Units have emerged as an efficient alternative to Central Processing Units for the computation of some problems.  ...  Both the routing computations as well as the schedule planning optimization can be done on the GPU.  ...  The main traffic controller computes on the GPU the All-Pairs Shortest Path problem in the planar graph using the FLoyd-Warshall algorithm (Floyd 1962) .  ... 
doi:10.1109/wsc.2015.7408239 dblp:conf/wsc/ChapuisESP15 fatcat:2he6j4ehxfb4bkzeezedjbzuou

Exploiting graphical processing units for data-parallel scientific applications

A. Leist, D. P. Playne, K. A. Hawick
2009 Concurrency and Computation  
We find a surprising variation in the performance that can be achieved on GPUs for our applications and discuss how these findings relate to past known effects in parallel computing such as memory speed-related  ...  We report on two further application paradigms -regular mesh field equations with unusual boundary conditions and graph analysis algorithms -that can also make use of GPU architectures.  ...  Scogings for helpful discussions on GPUs and on scientific programming.  ... 
doi:10.1002/cpe.1462 fatcat:zdr3r4kn25dqpl42ugle5qprea

Portable and efficient parallel computing using the BSP model

M.W. Goudreau, K. Lang, S.B. Rao, T. Suel, T. Tsantilas
1999 IEEE transactions on computers  
Index Terms: BSP, minimum spanning tree problem, models of parallel computation, N-body problem, parallel computing, parallel graph algorithms, shortest path problem.  ...  The Bulk-Synchronous Parallel (BSP) model was proposed by Valiant as a standard interface between parallel software and hardware.  ...  We acknowledge helpful discussions with Kai Li and Jim Philbin on the BSP library, and with J. P. Singh on N-body simulations.  ... 
doi:10.1109/12.780876 fatcat:k6xsoc775zfsxoznrrgepv2aru
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