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GORDIAN: VLSI placement by quadratic programming and slicing optimization

J.M. Kleinhans, G. Sigl, F.M. Johannes, K.J. Antreich
1991 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The global optimizations are performed by solving quadratic programming problems that possess unique global minima.  ...  Improved partitioning schemes for the stepwise refinement of the placement are introduced. The area utilization is optimized by an exhaustive slicing procedure.  ...  GLOBAL PLACEMENT BY QUADRATIC PROGRAMMING In each global optimization step, a quadratic programming problem is derived from the circuit connectivity (the net list) and from the dissection of the placement  ... 
doi:10.1109/43.67789 fatcat:3pqrdblkhjcrjooivwdsgw5bni

A Fast State Assignment Procedure for Large FSMs

Shihming Liu
1995 Proceedings - Design Automation Conference  
Experimental results are presented and compared with those of NOVA.  ...  This is an important problem in the high performance digital system design where added functionality often comes at the expense of a larger (and slower) FSM to control the system.  ...  Quadratic Programming Formulation The objective function of the global optimization step is then the weighted sum of the squared rubber band lengths of the edges of the given adjacency graph: where c ij  ... 
doi:10.1109/dac.1995.249968 fatcat:khj5qbuyu5fmdjpyoekl2b3swi

A fast state assignment procedure for large FSMs

Shihming Liu, Massoud Pedram, Alvin M. Despain
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
Experimental results are presented and compared with those of NOVA.  ...  This is an important problem in the high performance digital system design where added functionality often comes at the expense of a larger (and slower) FSM to control the system.  ...  Quadratic Programming Formulation The objective function of the global optimization step is then the weighted sum of the squared rubber band lengths of the edges of the given adjacency graph: where c ij  ... 
doi:10.1145/217474.217550 dblp:conf/dac/LiuPD95 fatcat:semkiou5mzbgpmghtplbdf4l2m

SeaPlace: Process Variation Aware Placement for Reliable Combinational Circuits against SETs and METs [article]

Kiarash Saremi, Hossein Pedram, Behnam Ghavami, Mohsen Raji, Zhenman Fang, Lesley Shannon
2021 arXiv   pre-print
Afterwards, a detailed placement algorithm (named SeaPlace-D) is proposed to increase the circuit reliability against METs by solving a linear programming optimization problem.  ...  The first proposed algorithm is a global placement method (called SeaPlace-G) that places the cells for hardening the circuit against SETs by solving a quadratic formulation.  ...  Antreich, “A field analysis of system-level effects of soft errors occurring “Gordian: Vlsi placement by quadratic programming and slicing in microprocessors used in information systems  ... 
arXiv:2112.04136v1 fatcat:t4ue6rnwkndltdh2xv7pfpcaoi

State assignment based on two-dimensional placement and hypercube mapping

S. Liu, M. Pedram, A.M. Despain
1997 Integration  
Experimental results are presented and compared against those of NOVA. These results demonstrate the effectiveness of the proposed approach.  ...  This is an important problem in digital system design where added functionality often comes at the expense of a larger (and slower) FSM to control the system.  ...  Quadratic Programming Formulation and Techniques The objective function of the global optimization step is then the weighted sum of the squared rubber band lengths of the edges of the given adjacency graph  ... 
doi:10.1016/s0167-9260(97)00027-8 fatcat:oawjlzc6bja6rdc3prt2tmzaue

Large-scale circuit placement

Jason Cong, Joseph R. Shinnerl, Min Xie, Tim Kong, Xin Yuan
2005 ACM Transactions on Design Automation of Electronic Systems  
The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools.  ...  The second part of the tutorial highlights the recent progress on large-scale circuit placement, including techniques for wirelength minimization, routability optimization, and performance optimization  ...  as an attempt at scalable placement by efficient nonlinear-programming.  ... 
doi:10.1145/1059876.1059886 fatcat:ji7ameibx5cqrefa5fmewiojci

Logic Synthesis [chapter]

2017 Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology  
Johannes, and K.J. Antreich, GORDIAN: VLSI placement by quadratic programming and slicing optimization, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10, 356-365, 1991. 14. K. Vorwerk, A.  ...  Quadratic algorithms took full advantage of this by deploying e cient quadratic optimization algorithms, intermixed with various types of partitioning schemes [13] .  ... 
doi:10.1201/9781315215112-13 fatcat:me52zpnxyfcczh3choo2p4zulm

Recent directions in netlist partitioning: a survey

Charles J Alpert, Andrew B Kahng
1995 Integration  
Combinatorial methods transform the partitioning problem into another type of optimization, e.g., based on network ows or mathematical programming.  ...  The paper concludes with a discussion of benchmarking in the VLSI CAD partitioning literature and some perspectives on more promising directions for future work.  ...  Boese and Bernhard M. Riess for their contributions to this review, and Albert Chung-Wen Tsao and Sudhakar Muddu for drawing gures. We also thank Martin D. F. Wong, Chung-Kuan Cheng, Pak K.  ... 
doi:10.1016/0167-9260(95)00008-4 fatcat:337iiybf3vhuzlybuub3wlvfiy

An industrial view of electronic design automation

D. MacMillen, R. Camposano, D. Hill, T.W. Williams
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper reviews the technologies, algorithms, and methodologies that have been used in EDA tools and the business impact of these technologies.  ...  The EDA business has profoundly influenced the integrated circuit (IC) business and vice-versa.  ...  quickly in systems like PROUD [117] and Gordian [68] .  ... 
doi:10.1109/43.898825 fatcat:hhk7zrepyfcyxgizvotqck7cei

Mixed block placement via fractional cut recursive bisection

A.R. Agnihotri, S. Ono, Chen Li, M.C. Yildiz, A. Khatkhate, Cheng-Kok Koh, P.H. Madden
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Half perimeter wire lengths are reduced by 29% on average, compared to a flow based on Capo and Parquet; compared to mPG-ms, wire lengths are reduced by 26% on average.  ...  This technique, which we refer to as a fractional cut, simplifies mixed block placement and also avoids a narrow region problem encountered in standard cell placement.  ...  Bazylevych and B. Swartz spurred much of this research. They would like to thank their colleagues at the IBM T. J. Watson Research Center and the IBM Austin Research Labs, and B.  ... 
doi:10.1109/tcad.2005.846363 fatcat:zqitk5ncabh6tjy3spvitlnqoa

Attractor-repeller approach for global placement

H. Etawil, S. Areibi, A. Wannelli
1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)  
The result is a placement with a great deal of overlap among the cells. To reduce cell overlap, the methodology iterates between global optimization and repartitioning of the placement area.  ...  Traditionally, analytic placement used linear or quadratic wirelength objective functions. Minimizing either formulation attracts cells sharing common signals (nets) together.  ...  Gordian [7] iterates between minimizing a quadratic objective function of wirelength and slicing the placement area.  ... 
doi:10.1109/iccad.1999.810613 dblp:conf/iccad/EtawilAV99 fatcat:juxmheddm5coxbik2qmkexr7gm

VEAP: Global optimization based efficient algorithm for VLSI placement

Kong Tianming, Hong Xianlong, Qiao Changge
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference  
In this paper we present a very simple, efficient while effective placement algorithm for Row-based VLSIs.  ...  This algorithm is based on strict mathematical analysis, and provably can find the global optima.  ...  The main loop of VEAP is formed by an iteration of global optimization and partitioning steps. In each step of global optimization, a mathematical programming problem is formed and solved.  ... 
doi:10.1109/aspdac.1997.600151 dblp:conf/aspdac/KongHQ97 fatcat:s523yyonpfg7fckdjehteelwyq

Boosting: min-cut placement with improved signal delay

A.B. Kahng, I.L. Markov, S. Reda
Proceedings Design, Automation and Test in Europe Conference and Exhibition  
Our method is generic and does not involve any timing analysis during or prior to placement.  ...  Empirically this approach does not significantly affect runtime, but reduces the worst negative slack and total negative slack of industrial benchmarks by up to 70% compared to Capo [5] and a leading industrial  ...  direction, that is, to linearize quadratic programs [16, 8, 15] .  ... 
doi:10.1109/date.2004.1269039 dblp:conf/date/KahngMR04 fatcat:bhka4p3ujnaadcalxhpifvqjtm

Multiscale Optimization in VLSI Physical Design Automation [chapter]

Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie, Yan Zhang
Multiscale Optimization Methods and Applications  
The enormous size and complexity of current and future integrated circuits (IC's) presents a host of challenging global, combinatorial optimization problems.  ...  We review recent advances in multiscale algorithms for three of them: partitioning, placement, and routing.  ...  However, a recent optimality study of VLSI placement algorithms shows a large gap between solutions from stateof-the-art placement algorithms and the true optima for a special class of synthetic benchmarks  ... 
doi:10.1007/0-387-29550-x_1 fatcat:6t2zhv7nkjfkblgt2i4hede2wa

Effective partition-driven placement with simultaneous level processing and global net views

Ke Zhong, S. Dutt
IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)  
Munich (termed FD-98 here), and 15.3% better than the multilevel placement technique Snap-On.  ...  In this paper we take a fresh look at the partition-driven placement (PDP) paradigm for standard-cell placement for wire-length minimization.  ...  Acknowledgements We thank Bharat Gali for implementing SeqLP, and the anonymous referees for their comments, which helped improve the presentation.  ... 
doi:10.1109/iccad.2000.896482 dblp:conf/iccad/ZhongD00 fatcat:qop43umgxfay5mqj7bceq3ulhi
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