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Functional formal verification on designs of pSeries microprocessors and communication subsystems

R. M. Gott, J. R. Baumgartner, P. Roessler, S. I. Joe
2005 IBM Journal of Research and Development  
This paper discusses our experiences and results in applying functional formal verification (FFV) techniques to the design of the IBM pSeriest microprocessor and communication subsystem.  ...  Overall, numerous complex design defects were discovered using formal techniques across the microprocessor and communication subsystem, many of which would likely have escaped to the test floor.  ...  This paper details the experience of deploying formal methods on the pSeries POWER5 processor and the communication subsystem, which consists of the pSeries High Performance Switch (HPS) and the Switch  ... 
doi:10.1147/rd.494.0565 fatcat:fo5pfj5ckjfxde3gdiotaochsa

Using microcode in the functional verification of an I/O chip

S. P. Goldman, L. M. Mohr, D. R. Smith
2005 IBM Journal of Research and Development  
Functional verification may be performed at the unit, chip, subsystem, and/or system levels. A unit is a logical partition of the design which performs a specific function.  ...  A subsystem is a collection of two or more chips that communicate directly with each other.  ... 
doi:10.1147/rd.494.0581 fatcat:veirbjo7ljdzzlaakhp56vkxby

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems

J. M. Ludden, W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson, B.-L. Chu, M. L. Behm, J. R. Baumgartner, R. D. Peterson, J. Abdulhafiz, W. E. Bucy, J. H. Klaus (+13 others)
2002 IBM Journal of Research and Development  
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems This paper describes the methods and simulation techniques used to verify the microarchitecture design and functional  ...  Multi-unitlevel verification, performed on storage and I/O components as well as on the processor, confirmed architectural compliance for each of the chips and subsystems.  ...  Functional formal verification Functional formal verification (FFV) is the process of proving the correct functionality of a model.  ... 
doi:10.1147/rd.461.0053 fatcat:474llttpkvghngwg4q6veuhvqq

Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems

D. W. Victor, J. M. Ludden, R. D. Peterson, B. S. Nelson, W. K. Sharp, J. K. Hsu, B.-L. Chu, M. L. Behm, R. M. Gott, A. D. Romonosky, S. R. Farago
2005 IBM Journal of Research and Development  
This paper describes the methods and simulation techniques used to verify the functional correctness and performance attributes of the IBM POWER5e microprocessor and the eServere p5 systems based on it  ...  In parallel with the mainline functional validation, verification of reliability functions and performance attributes also had increased focus for the POWER5 design.  ...  low-end iSeries and pSeries spaces [1] .  ... 
doi:10.1147/rd.494.0541 fatcat:jnkly5gj3zfphcfjxb5quh2fym

A performance methodology for commercial servers

S. R. Kunkel, R. J. Eickemeyer, M. H. Lipasti, T. J. Mullins, B. O'Krafka, H. Rosenberg, S. P. VanderWiel, P. L. Vitale, L. D. Whitley
2000 IBM Journal of Research and Development  
Creation of input data for performance models on the basis of measured workload information.  ...  This step in the methodology must overcome the operating environment differences between the instance of the measured system under test and the target system design to be modeled. 4.  ...  Acknowledgments We would like to acknowledge Jack Randolph for his years of work on the PMCs and tracing port of the processor chip, David Pease for the development of the interface hardware to collect  ... 
doi:10.1147/rd.446.0851 fatcat:ebdeieh2ifcihmhr6jx7ytzjwq

Configurable system simulation model build comprising packaging design data

H.-W. Anderson, H. Kriese, W. Roesner, K.-D. Schubert
2004 IBM Journal of Research and Development  
A high-end eServer consists of multiple microprocessor chips packaged with additional chips on a multichip module.  ...  In conjunction with memory and various I/O cards, this module is mounted on a card called a processor book, and a few of those cards on a board finally represent a major part of the system.  ...  Functional verification of the packaging is therefore one of the tasks performed during system verification.  ... 
doi:10.1147/rd.483.0367 fatcat:seslo5hnxjf2xbokecsjl73tby

5. Performance Evaluation and Modeling of Ultra-Scale Systems [chapter]

Leonid Oliker, Rupak Biswas, Rob Van der Wijngaart, David Bailey, Allan Snavely
2006 Parallel Processing for Scientific Computing  
The memory hierarchy consists of 128 FP registers and three on-chip data caches (32KB L1, 256KB L2, and 6MB L3).  ...  The SGI Altix is designed as a cache-coherent, shared-memory multiprocessor system.  ...  They also gratefully acknowledge Kengo Nakajima for reviewing the material on geophysics. L. Oliker and D. Bailey are supported by OASCR in the U.S.  ... 
doi:10.1137/1.9780898718133.ch5 fatcat:jyybuvlpbrf3ficv565cy7jvua

D5.3: Updated Best Practices for HPC Procurement and Infrastructure

Andreas Johansson
2014 Zenodo  
The work package opens the possibility of closer co-operation between the PRACE community and infrastructure vendors, e.g.  ...  Task 2 – Best practices for designing and operating power efficient HPC centre infrastructures – has continued the production of white papers which explore specific topics related to HPC data centre design  ...  in Engineering and coordinator of the project, the group IKM of the LUH, the Gottfried Wilhelm Leibniz Universitaet Hannover in Germany and the National Technical University of Athens in Greece and institutions  ... 
doi:10.5281/zenodo.6572433 fatcat:cwiqrgf33jajjjvhubky4f6rau