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Functional and Performance Analysis of Network-on-Chips Using Actor-based Modeling and Formal Verification

Zeinab Sharifi, Mahdi Mosaffa, Siamak Mohammadi, Marjan Sirjani
2014 Electronic Communications of the EASST  
We present a formal model for two-dimensional mesh GloballyAsynchronous Locally Synchronous (GALS) NoCs with four-phase handshakecommunication protocol, using the actor-based modeling language Rebeca.  ...  Network on Chip (NoC) has emerged as a promising architecture paradigmfor todays many-core systems.  ...  In this paper, we use formal methods to perform functional verification and performance estimation on GALS NoC on the same model.  ... 
doi:10.14279/tuj.eceasst.66.890 dblp:journals/eceasst/sharifiMMS13 fatcat:qaodfshiqjcdle2zqe6grxxydi

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Fateh Boutekkouk
2018 International Journal of Recent Contributions from Engineering, Science & IT  
Network-On-Chip (NOC) is an emerging paradigm to surmount traditional bus based Systems-On-Chip (SOC) limits especially scalability and communication performances.  ...  On the other hand, the application of formal methods to on-chip communication infrastructures has recieved more attention.  ...  Using an actor based modeling language; they efficiently mapped the constituents of GALS NOC to actor model.  ... 
doi:10.3991/ijes.v6i4.9416 fatcat:7fljmcayfvdgpd7v3d4vt7lkvu

Developing architectural platforms: a disciplined approach

A. Mihal, C. Kulkarni, M. Moskewicz, M. Tsai, N. Shah, S. Weber, Yujia Jin, K. Keutzer, K. Vissers, C. Sauer, S. Malik
2002 IEEE Design & Test of Computers  
Architects construct network topologies using an extendable library of network-on-a-chip components.  ...  As with the microarchitecture and memory views, we based the multiprocessor view on a formal computation model that gives the model functional semantics.  ... 
doi:10.1109/mdt.2002.1047739 fatcat:3od3meg5gbaabdlflfycfb2cy4

Performance Estimation of HEVC/h.265 Decoder in a Co-Design Flow with SADF-FSM Graphs

Habib Smei, Abderrazak Jemai, Kamel Smiri
2017 International Journal of Communications, Network and System Sciences  
In the modeling step, a high-level performance analysis is performed to find an optimal balance between the decoding efficiency and the implementation cost, thereby reducing the complexity of the system  ...  In this paper, the HEVC/h.265 video decoder is modeled with SADF based FSM in order to solve problems of placing and scheduling this application on an embedded architecture.  ...  It contains on the same chip two components. The first is a dual-core ARM Cortex MPCore based on a high-performance processing system (PS).  ... 
doi:10.4236/ijcns.2017.1011016 fatcat:3mmaqu5sj5h3bkaacx6qiz4xni

A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications [chapter]

Seyed-Hosein Attarzadeh-Niaki, Ekrem Altinel, Martijn Koedam, Anca Molnos, Ingo Sander, Kees Goossens
2016 Model-Implementation Fidelity in Cyber Physical System Design  
The models are executable, which enables early detection of specification errors, and include the formal properties of the applications based on well-defined models of computation.  ...  We define a formal modeling framework as a suitable entry point for application design.  ...  We plan to enrich the flow by supporting additional MoCs such as the Synchronous (SY) MoC for control-oriented behavior and also aim at a mixedcriticality design flow.  ... 
doi:10.1007/978-3-319-47307-9_6 fatcat:2fu5nuwlkvg37nwjcsroup2uxq

GRL: A Specification Language for Globally Asynchronous Locally Synchronous Systems [chapter]

Fatma Jebali, Frédéric Lang, Radu Mateescu
2014 Lecture Notes in Computer Science  
In this paper, we present a new language, called GRL (GALS Representation Language) designed to model GALS systems in an abstract and versatile manner for the purpose of formal verification.  ...  Most formalisms and design tools support either the synchronous paradigm or the asynchronous paradigm but rarely combine both, which requires an intricate modeling of GALS systems.  ...  The first one is a parser for GRL (2000 lines), developed using the SYNTAX and Lotos NT compiler construction technology [10] , which performs lexical and syntax analysis, type checking, binding analysis  ... 
doi:10.1007/978-3-319-11737-9_15 fatcat:b3lgksjgk5hzbew6fokf3vcopu

Dataflow formalisation of real-time streaming applications on a Composable and Predictable Multi-Processor SOC

Andrew Nelson, Kees Goossens, Benny Akesson
2015 Journal of systems architecture  
To efficiently execute applications, modern embedded systems contain Globally Asynchronous Locally Synchronous (GALS) processors, network on chip, DRAM and SRAM memories, and system software, e.g. microkernel  ...  The dataflow formalisation is composable (i.e. independent for each real-time application), conservative, models the impact of GALS on performance, and correctly predicts trends, such as application speed-up  ...  Acknowledgements This work was partially funded by projects EU FP7 288008 T-CREST and 288248 Flextiles, CA505 BENEFIC, CA703 OpenES, ARTEMIS-2013-1 621429 EMC2, 621353 DEWI, and the European Social Fund  ... 
doi:10.1016/j.sysarc.2015.04.001 fatcat:wjjajmj5hnbs5d4qc3ebkugcu4

On Time Actors [chapter]

Marjan Sirjani, Ehsan Khamespanah
2016 Lecture Notes in Computer Science  
Timed Rebeca is equipped with analysis techniques based on the standard semantics of timed systems, and also an innovative event-based semantics that is tailored for timed actor models.  ...  Timed Rebeca is an actor-based modeling language which is designed for modeling and analyzing of event-based and asynchronous systems with time constraints.  ...  Timed Rebeca in Practice Timed Rebeca is used in several applications such as modeling and analysis of routing algorithms for Network on Chips (NOCs) [12, 14] , and schedulability analysis of wireless  ... 
doi:10.1007/978-3-319-30734-3_25 fatcat:rcgkhc6l2zcqte24or54k2tvte

Virtual execution platforms for mixed-time-criticality systems

Kees Goossens, Ashkan Beyranvand Nejad, Andrew Nelson, Shubhendu Sinha, Arnaldo Azevedo, Karthik Chandrasekar, Manil Dev Gomony, Sven Goossens, Martijn Koedam, Yonghui Li, Davit Mirzoyan, Anca Molnos
2013 ACM SIGBED Review  
SOC functionality and (real-time) performance is verified after all applications have been integrated.  ...  Systems on chip (SOC) contain multiple concurrent applications with different time criticality (firm, soft, non realtime).  ...  This work was partially funded by projects EU FP7 288008 T-CREST and 288248 Flextiles, Catrene CA104 Cobra, and NL STW 10346 NEST.  ... 
doi:10.1145/2544350.2544353 fatcat:lxmodfh25jdrpifqc727rnuija

A compilation flow for parametric dataflow

Mickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jérôme Martin, Henri-Pierre Charles
2014 Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14  
Built on the LLVM compiler infrastructure, it offers an actor based C++ programming model to describe parametric graphs, a compilation front-end providing graph analysis features, and a retargetable back-end  ...  These models permit to express inherent application parallelism, as well as analysis for both verification and optimization.  ...  Main configuration and control of the chip is done by an ARM CPU, and communications between blocks use a 2D-mesh network on chip.  ... 
doi:10.1145/2656106.2656110 dblp:conf/cases/DardaillonMRMC14 fatcat:2mgcsosqlzejpdtvwyru5jasbm

Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications [article]

Hasan Al Shaikh, Mohammad Bin Monjil, Shigang Chen, Navid Asadizanjani, Farimah Farahmandi, Mark Tehranipoor, Fahim Rahman
2022 arXiv   pre-print
The proposed DT framework leverages these relationships and relational learning to achieve Forward and Backward Trust Analysis functionalities enabling security aware management of the entire lifecycle  ...  We posit that if there is a malicious or unintentional breach of security policies of a device, it will be reflected in the form of anomalies in the traditional design, verification and testing activities  ...  verification, formal verification methods can be useful.  ... 
arXiv:2205.10962v2 fatcat:gzlhrvansna6xhegfjh4agw6ne

Predictable dynamic embedded data processing

Marc Geilen, Sander Stuijk, Twan Basten
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
A formal, compositional model is used to exploit Pareto-optimal trade-offs in the system use.  ...  In this paper, we present a model-driven approach that combines model-based design and synthesis with development of platforms that support predictable, repeatable, composable realizations and a run-time  ...  We use a tile-based chip multiprocessor system, where the tiles are connected by a network-on-chip.  ... 
doi:10.1109/samos.2012.6404194 dblp:conf/samos/GeilenSB12 fatcat:oskdckwjujexxhj5dyraehmuqa

A New Compilation Flow for Software-Defined Radio Applications on Heterogeneous MPSoCs

Mickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jérôme Martin, Henri-Pierre Charles
2016 ACM Transactions on Architecture and Code Optimization (TACO)  
Based on this formalism, we provide a new buffer size verification method using model checking which can be performed when mapping dataflow graph on MPSoCs.  ...  Main configuration and control of the chip is done by an ARM CPU, and communications between blocks use a 2D-mesh network on chip.  ... 
doi:10.1145/2910583 fatcat:zvgvyrsahrbjlkretgonnbnbk4

Industrial Cyber-Physical Systems – iCyPhy [chapter]

Amit Fisher, Clas A. Jacobson, Edward A. Lee, Richard M. Murray, Alberto Sangiovanni-Vincentelli, Eelco Scholte
2014 Complex Systems Design & Management  
ICyPhy is a pre-competitive industry-academic partnership focused on architectures, abstractions, technologies, methodologies, and supporting tools for the design, modeling, and analysis of large-scale  ...  The focus is on cyber-physical systems, which combine a cyber side (computing and networking) with a physical side (e.g., mechanical, electrical, and chemical processes).  ...  One of the key challenges is to integrate actor-oriented models with practical and realistic notions of time.  ... 
doi:10.1007/978-3-319-02812-5_2 dblp:conf/csdm/FisherJLMSS13 fatcat:pnb2o3qkbfcwjoqmbw6syvky5i

Synchronous Programming (Dagstuhl Seminar 13471)

Stephen A. Edwards, Alain Girault, Klaus Schneider, Marc Herbstritt
2014 Dagstuhl Reports  
techniques, software and hardware architectures, as well as extensions, transformations, and interfaces to other models of computations, in particular to asynchronous and hybrid systems.  ...  For this reason, the synchronous composition is deterministic, which is a great advantage concerning predictability, verification of system design, and embedded code generation.  ...  The concept of pressure-based progress control is explained and the coordination of pressure via state-machine based synchronisers is discussed. This is work in progress.  ... 
doi:10.4230/dagrep.3.11.117 dblp:journals/dagstuhl-reports/EdwardsGS13 fatcat:b7aq6w2q4fawjjqtlfleujr3gi
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