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Formal verification of a fully IEEE compliant floating point unit [article]

Christian Jacobi, Universität Des Saarlandes, Universität Des Saarlandes
for automatic verification.  ...  If the PVS function has integer parameters to represent parameterized circuits (e.g, the carry-chain adder from section 2.2), a Verilog module for each different occurring parameterization is generated  ...  Most notably, the decomposition theorem of rounding allows for the decomposition of the rounding hardware into smaller parts, and the concept of αequivalence makes the decomposition of the FPU into computational  ... 
doi:10.22028/d291-25704 fatcat:poss73nl5bg6zh5o6kanqrfose