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with Critical Path Analysis ◆ Prerequisite is a dependence graph representing timing constraints ◆ Simple for small system with few events ◆ Becomes much harder for bigger systems ◆ Algorithmically map ... problems ◆ Analysis can automatically identify them ◆ Predict performance if the paths are broken ◆ Example output ◆ TCP Stream between two systems with large link delay Most critical edges (time ...doi:10.1109/ispass.2008.4510739 dblp:conf/ispass/SaidiBRM08 fatcat:pnocm5jet5cdxgjoi6r7qbyq7i
In this paper, the direct application of the extension principle leads to a proposition that must be satisfied in fuzzy critical path analysis. ... However, the fuzzy version of the forward recursion has been widely proposed as an approach for determining the fuzzy set of critical path lengths. ... path analysis from the crisp to the fuzzy domain, any proposed fuzzy critical path analysis approach should provide results that are consistent with it. ...doi:10.5121/ijfls.2016.6204 fatcat:56aerrsh5bbltlabgarlezh7jy
It has long been recognized that it can be tedious and even infeasible for system administrators to figure out critical security problems residing in full attack graphs, even for small-sized enterprise ... in-depth analysis. ... of the full attack graph.Therefore we believe in order to bring the analysis of generated attack graphs into a more practical level and also help the system administrator (SA) perform in-depth analysis ...doi:10.1145/2076732.2076738 dblp:conf/acsac/HuangZOPS11 fatcat:jcydpzeprzdgjjovaqhu6ugeme
We present a methodology for identifying end-to-end critical paths across software and simulated hardware in complex networked systems. ... By modeling systems as collections of state machines interacting via queues, we can trace critical paths through multiplexed processing engines, identify when resources create bottlenecks (including abstract ... BACKGROUND Critical-path analysis (CPA) has been applied in many domains to find bottlenecks in complex, concurrent systems. ...doi:10.1145/1555815.1555800 fatcat:hypfckpyyzf7tl3m2soi3abete
We present a methodology for identifying end-to-end critical paths across software and simulated hardware in complex networked systems. ... By modeling systems as collections of state machines interacting via queues, we can trace critical paths through multiplexed processing engines, identify when resources create bottlenecks (including abstract ... BACKGROUND Critical-path analysis (CPA) has been applied in many domains to find bottlenecks in complex, concurrent systems. ...doi:10.1145/1555754.1555800 dblp:conf/isca/SaidiBRM09 fatcat:aphddny6dnc4vk2njw3op6ummi
Naše More (Dubrovnik)
Network Planning Method in Optimizing Vessel Utilization – Laytime Calculation
Network Planning Method in Optimizing Vessel Utilization – Laytime Calculation
It was illustrated with a hypothetical example of applying the network planning method in optimization of transhipment of containers in terms of time only, although the full contribution of network planning ... Critical path and activities that it consists of must be monitored with special attention, so for this reason the time analysis is named the critical path method 2 . ... Full paths in the network diagram do not have to have the same duration. ...doi:10.17818/nm/2018/3.3 fatcat:vikqamtqurbgddskoutivc5tom
Proceedings. 42nd Design Automation Conference, 2005.
of significant reordering of speed path criticality and a 36.4% increase in worst-case slack. ... The technique relies on the extraction of residual OPC errors from placed and routed full chip layouts to derive actual (i.e., calibrated to silicon) CD values that are then used in timing analysis and ... Then a full-chip timing analysis is performed using commercial tools and the top critical paths are reported. ...doi:10.1109/dac.2005.193834 fatcat:7issndgmzbbhxkajotmun32ymy
of significant reordering of speed path criticality and a 36.4% increase in worst-case slack. ... The technique relies on the extraction of residual OPC errors from placed and routed full chip layouts to derive actual (i.e., calibrated to silicon) CD values that are then used in timing analysis and ... Then a full-chip timing analysis is performed using commercial tools and the top critical paths are reported. ...doi:10.1145/1065579.1065676 dblp:conf/dac/YangCS05 fatcat:xoltqxidn5fk3noyy65sva7ja4
On the equilibrium paths, there are identified critical points which contribute to understanding and quantification of stability processes in a nonlinear system. ... The paper describes multidisciplinary problems of the analysis of limit states of nonlinear systems. ... Along a static equilibrium path of a conservative system, transition from stability to instability can occur at critical points only. ...doi:10.1051/matecconf/20167604026 fatcat:i6kw43paongltohswebljwhjte
Table 1 shows the results of the analyses for linear alternate path analysis for full service load and Eq. 1 conditions. ... ALTERNATE PatHs ANALYSES The 12 by 12 bay hypothetical space truss was analyzed using both linear and nonlinear alternate path analysis methods. In each analysis, only one member was removed. ...
Power consumption of digital systems is an important issue in nanoscale technologies and growth of process variation makes the problem more challenging. ... Index Terms-Adder structures, architecture, deep pipeline, massive parallel, statistical static timing analysis (SSTA), ultra low energy, variation-aware. ... Variation of each cell is assumed as a normal (Gaussian) variable  ,  (2) and (3) 1  μ Critical−path = n i=1 μ i , δ 2 Critical−path = n i=1 δ 2 i (2) Delay Critical−path = μ Critical−path ...doi:10.1109/tvlsi.2015.2426113 fatcat:un7mmh54gfhyld33whj6fvbh3y
We then present some algorithmic modifications that reduce post-compilation critical path delay by an average of 40%. ... full timing analysis Figure 6 .Figure 7 . 67 Stability Wire cost and post-routing critical path delay comparison for all examined tools Table 1 . 1 Benefits of frequent static timing analysis -Conventional ... In Figure 1 we believe that we will make the system better if we move block a to reduce the delay on the critical path (a, c). ...doi:10.1145/1391469.1391480 dblp:conf/dac/EguroH08 fatcat:po3ek3j4lfeo5p62h36xofmt3m
In other words, the critical path is the global execution path that inflicts wait operations on other nodes without itself being stalled. ... The critical path is one of the fundamental runtime characteristics of a parallel program. It identifies the longest execution sequence without wait delays. ... Second, we use offline, post-mortem analysis to merge the local subgraphs into a global graph and extract the critical path. The architecture of our system is illustrated in Figure 4 . ...doi:10.1109/clustr.2005.347035 dblp:conf/cluster/Schulz05 fatcat:px2p3wlt5jae7ffhtykjl2mtaq
path alone. ... This paper presents a tool flow to perform SRAM wide statistical analysis subject to combinations of global litho and local variability components. ... Critical Path vs. Full Memory Analysis One attempt to derive the worst case behavior of a memory might be a corner simulation of the critical path netlist. ...doaj:49a963f883ce435cbfabd46eb5005fe8 fatcat:qll3ixy6xzfkvbz6orqdjn4fne
To obtain a list with all critical paths, a path-based timing analysis is required which is not feasible for medium-to-large size circuits due to the complexity of the analysis  . ... Industrial timing analysis tools  can report the most critical path that includes any specific nodes, based on the block-based timing analysis. ... He is currently a Full Professor of Real-Time Embedded Systems with the Electronic Systems Group, Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands. ...doi:10.1109/tvlsi.2019.2895972 fatcat:6zzknihzpbcmhkxdzq7q3ybcxi
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