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From signal temporal logic to FPGA monitors

Stefan Jaksic, Ezio Bartocci, Radu Grosu, Reinhard Kloibhofer, Thang Nguyen, Dejan Nickovie
2015 2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)  
We propose novel algorithms for translating signal temporal logic (STL) assertions to hardware runtime monitors implemented in field programmable gate array (FPGA).  ...  In order to accommodate to this hardware specific setting, we restrict ourselves to past and bounded future temporal operators interpreted over discrete time.  ...  FROM SIGNAL TEMPORAL LOGIC TO HARDWARE MONITORS A.  ... 
doi:10.1109/memcod.2015.7340489 dblp:conf/memocode/JaksicBGKNN15 fatcat:odfwzys3gnhaxknz5gsmm4pya4

Runtime Analysis with R2U2: A Tool Exhibition Report [chapter]

Johann Schumann, Patrick Moosbrugger, Kristin Y. Rozier
2016 Lecture Notes in Computer Science  
The FPGA realization enables R2U2 to monitor complex cyber-physical systems without any overhead or instrumentation of the flight software.  ...  The FPGA realization enables R2U2 to monitor complex cyber-physical systems without any overhead or instrumentation of the flight software.  ...  R2U2 models consist of temporal logic formulas, Bayesian networks, and specifications of signal-preprocessing and filtering.  ... 
doi:10.1007/978-3-319-46982-9_35 fatcat:st7uhuij7bf4rlypmsckt7j7xm

In-circuit temporal monitors for runtime verification of reconfigurable designs

Tim Todman, Stephan Stilkerich, Wayne Luk
2015 Proceedings of the 52nd Annual Design Automation Conference on - DAC '15  
We present designs for in-circuit monitoring of custom hardware designs implemented in reconfigurable hardware. The monitors check hardware designs against temporal logic specifications.  ...  Compared to previous work, which used custom hardware to monitor software, our designs can run at higher speeds and make better use of hardware resources, such as shift registers and embedded memory blocks  ...  The research leading to these results has received funding from the European Union Seventh framework programme (grant agreement number 318521) and the UK Engineering and Physical Sciences Research Council  ... 
doi:10.1145/2744769.2744856 dblp:conf/dac/TodmanSL15 fatcat:wf5cjj37k5e6hc4ioqa6vch2iq

Applying Runtime Monitoring for Automotive Electronic Development [chapter]

Konstantin Selyunin, Thang Nguyen, Ezio Bartocci, Radu Grosu
2016 Lecture Notes in Computer Science  
In the later phase when a prototype or a product is available, the runtime monitors from the concept development are reused for synthesis into FPGA for monitoring the implementation correctness of the  ...  Starting with concept development, runtime monitors are generated from the product requirements and then embedded in a chip simulation to track the specification compliance at an early stage.  ...  ICT COST Action IC1402 on Runtime Verification beyond Monitoring (ARVI).  ... 
doi:10.1007/978-3-319-46982-9_30 fatcat:wkxpokdgh5e57nt3t3dr7xurmm

The HARMONIA Project: Hardware Monitoring for Automotive Systems-of-Systems [chapter]

Thang Nguyen, Ezio Bartocci, Dejan Ničković, Radu Grosu, Stefan Jaksic, Konstantin Selyunin
2016 Lecture Notes in Computer Science  
Observers embedded on FPGA hardware will be generated from assertions, and used for monitoring automotive designs emulated on hardware.  ...  The aim of the HARMONIA project is to provide a framework for assertion-based monitoring of automotive systems-of-systems with mixed criticality.  ...  Ezio Bartocci and Dejan Ničković acknowledge also the support of the EU ICT COST Action IC1402 on Runtime Verification beyond Monitoring (ARVI).  ... 
doi:10.1007/978-3-319-47169-3_28 fatcat:fwwhfmjp3nhljbl5rn2udf2nuy

Runtime Observer Pairs and Bayesian Network Reasoners On-board FPGAs: Flight-Certifiable System Health Management for Embedded Systems [chapter]

Johannes Geist, Kristin Y. Rozier, Johann Schumann
2014 Lecture Notes in Computer Science  
In this paper, we show how to instantiate and implement temporal logic runtime observers and Bayesian network diagnostic reasoners that use the observers' outputs, on-board a field-standard Field Programmable  ...  We run our system with a full set of real flight data from NASA's Swift UAS, and highlight a case where our runtime SHM framework would have been able to detect and diagnose a fault from subtle evidence  ...  We require the temporal logic observer pairs for efficient temporal reasoning but since temporal monitors don't make decisions, Bayesian reasoning is required in conjunction with our temporal logic observer  ... 
doi:10.1007/978-3-319-11164-3_18 fatcat:piehgceiznaptfbmuxwlbx73o4

R2U2: monitoring and diagnosis of security threats for unmanned aerial systems

Patrick Moosbrugger, Kristin Y. Rozier, Johann Schumann
2017 Formal methods in system design  
R2U2 uses runtime observer pairs for Linear and Metric Temporal Logics for property monitoring and Bayesian networks for diagnosis of system health during runtime.  ...  R2U2 is designed to continuously monitor inputs from on-board components such as the GPS, the ground control station, other sensor readings, actuator outputs, and flight software status.  ...  Signals from the flight computer and communication buses are transmitted to the R2U2 monitoring device that continuously monitors these signals using signal processing, temporal logic observers and Bayesian  ... 
doi:10.1007/s10703-017-0275-x fatcat:3ykk6afjmnfqlb66rqpiz3zkbi

R2U2: Monitoring and Diagnosis of Security Threats for Unmanned Aerial Systems [chapter]

Johann Schumann, Patrick Moosbrugger, Kristin Y. Rozier
2015 Lecture Notes in Computer Science  
R2U2 uses runtime observer pairs for Linear and Metric Temporal Logics for property monitoring and Bayesian networks for diagnosis of system health during runtime.  ...  R2U2 is designed to continuously monitor inputs from on-board components such as the GPS, the ground control station, other sensor readings, actuator outputs, and flight software status.  ...  Signals from the flight computer and communication buses are transmitted to the R2U2 monitoring device that continuously monitors these signals using signal processing, temporal logic observers and Bayesian  ... 
doi:10.1007/978-3-319-23820-3_15 fatcat:iw5ktaseivhypkd57k7bl6he5e

Hardware runtime verification of embedded software in SoPC

Dimitry Solet, Jean-Luc Bechennec, Mikaol Briday, Sebastien Faucou, Sebastien Pillement
2016 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)  
These monitors are synthesised from a formal specification of the expected behavior of the system expressed as a set of past-time linear temporal logic (ptLTL) formulas.  ...  To do so, a minimal instrumentation of the software is used to send events to a set of monitors implemented in the FPGA.  ...  Monitors take these propositions to evaluate the given specifications. Monitors are designed from a Linear-time Temporal Logic (LTL) property.  ... 
doi:10.1109/sies.2016.7509425 dblp:conf/sies/SoletBBFP16 fatcat:brg3xmsvqzfzjnizbl6hq4wdoi

FPGA implementation of a ZigBee wireless network control interface to transmit biomedical signals

M A Gómez López, C B Goy, P C Bolognini, M C Herrera
2011 Journal of Physics, Conference Series  
Using an USB port, the COORDINATOR sends the signals to a personal computer for displaying. Each functional block of control interface was assessed by means of temporal diagrams.  ...  FPGA internal memory stores 8-bit signals with which the control interface prepares the information packets.  ...  Acknowledgments This work was supported in part by grants from the UNT Research Council (CIUNT), 26/E422-3 Research Program and INSIBIO (CONICET).  ... 
doi:10.1088/1742-6596/332/1/012007 fatcat:xik7fdte7rcahampb4ywupwmei

Towards Real-time, On-board, Hardware-supported Sensor and Software Health Management for Unmanned Aerial Systems

Johann Schumann, Kristin Y. Rozier, Thomas Reinbacher, Ole J. Mengshoel, Timmy Mbaya, Corey Ippolito
2020 International Journal of Prognostics and Health Management  
Our approach to SHM is three-pronged, providing: (1) real-time monitoring of sensor and software signals; (2) signal analysis, preprocessing, and advanced on-the-fly temporal and Bayesian probabilistic  ...  Our implementation provides a novel approach of combining modular building blocks, integrating responsive runtime monitoring of temporal logic system safety requirements with model-based diagnosis and  ...  We would like to thank the anonymous reviewers for their detailed feedback to improve this paper.  ... 
doi:10.36001/ijphm.2015.v6i1.2243 fatcat:akm2xbrv4jeqtj5yqd5mytfs2y

Interfacing the Analog Camera with FPGA Board for Real-time Video Acquisition

Sanjay Singh, Anil K Saini, Ravi Saini
2014 International Journal of Image Graphics and Signal Processing  
The necessary control logics for video acquisition and video display are designed using VHDL and Verilog, simulated in ModelSim, and synthesized using Xilinx ISE 12.1.  ...  Advances in FPGA technology have dramatically increased the use of FPGAs for computer vision applications.  ...  ACKNOWLEDGMENT The authors express their deep sense of gratitude to Dr. Chandra Shekhar, Director CSIR-CEERI for encouraging research and development activities. Authors would like to thanks Dr.  ... 
doi:10.5815/ijigsp.2014.04.04 fatcat:lh4naarxkrgtroa5us26bphzrm

Rapidly Adjustable Non-intrusive Online Monitoring for Multi-core Systems [chapter]

Normann Decker, Philip Gottschling, Christian Hochberger, Martin Leucker, Torben Scheffel, Malte Schmitz, Alexander Weiss
2017 Lecture Notes in Computer Science  
The necessary computing performance is provided by an FPGA-based event processing system.  ...  This paper presents an approach for rapidly adjustable embedded trace online monitoring of multi-core systems, called RETOM.  ...  Because of that, TeSSLa uses asynchronous streams as underlaying model, similar to Signal Temporal Logic (STL) [20] .  ... 
doi:10.1007/978-3-319-70848-5_12 fatcat:ejtphr7w3zeh7obawxla2cqkee

Diffuse Correlation Spectroscopy Analysis Implemented on a Field Programmable Gate Array

Wei Lin, David R. Busch, Chia Chieh Goh, James Barsi, Thomas F. Floyd
2019 IEEE Access  
This analyzer implements the DCS curving fitting algorithm on digital logic circuit using Field Programmable Gate Array (FPGA) technology.  ...  In combination with previously described FPGA implementations of auto-correlators, this hardware analyzer can provide a complete device-on-a-chip solution for DCS signal processing.  ...  When the control module receives the STA signal from the MSE pipeline, it deactivates the CTL signal to put the MSE pipeline on hold. D.  ... 
doi:10.1109/access.2019.2938085 pmid:32457822 pmcid:PMC7249994 fatcat:6cctzxj7vnbqfg6bzcgsrd3w6u

A FPGA real-time model of single and multiple visual cortex neurons

Guangxing Li, Vargha Talebi, Ahmad Yoonessi, Curtis L. Baker
2010 Journal of Neuroscience Methods  
Here we present a Field Programmable Gate Array (FPGA)-based spiking model of visual cortex neurons, which has the ability to simulate three independent neurons and output analog spike waveform signals  ...  The model can be easily constructed from a small number of inexpensive commercially available parts, and is straightforward to operate.  ...  -348949-2007 to V.T.  ... 
doi:10.1016/j.jneumeth.2010.07.031 pmid:20705096 fatcat:fqeogtyc3ngm5mg7rvsd4javii
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