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Flexible LDPC Decoder Architectures

Muhammad Awais, Carlo Condo
2012 VLSI design (Print)  
However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable  ...  This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders.  ...  As a case of study, we focused our research on the WiMAX codes.  ... 
doi:10.1155/2012/730835 fatcat:sxvzpnz6ufgtblq2dn3p3m7wyi

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic
2017 International Journal of Reconfigurable Computing  
Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA.  ...  To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite.  ...  Acknowledgments The authors would like to thank the Department of Electrical and Computer Engineering, Rutgers University, NJ, USA, and the National Instruments Corporation, Austin, TX, USA, for their  ... 
doi:10.1155/2017/3689308 fatcat:33ugoq5vyjbzrgtwvk7aaus64i

Design and Architectures for Signal and Image Processing

Markus Rupp, Ahmet T. Erdogan, Bertrand Granado
2009 EURASIP Journal on Embedded Systems  
This Special Issue of the EURASIP Journal of embedded systems is intended to present innovative methods, tools, design methodologies, and frameworks for algorithm-architecture matching approach in the  ...  Today, typical sequential design flows are in use and they are reaching their limits due to:  ...  Taking the LDPC codes for the wireless local area network (IEEE 802.11n) as a case study, a detailed analysis of the performance attained with the proposed techniques and architectures is reported, and  ... 
doi:10.1155/2009/674308 fatcat:l2npgnxwavb3xgmedjdzwklv6y

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case

G. Falcao, M. Owaida, D. Novo, M. Purnaprajna, N. Bellas, C.D. Antonopoulos, G. Karakonstantis, A. Burg, P. Ienne
2012 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines  
Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs.  ...  In this paper we propose a new design flow based on OpenCL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration  ...  FPGA Results Tables I and II detail performance and area results of the two LDPC kernels implemented on a Virtex-6 LX760 FPGA.  ... 
doi:10.1109/fccm.2012.46 dblp:conf/fccm/FalcaoONPBAKBI12 fatcat:bh5ywb3csvdafai7sorxzkqq5a

A Survey Of Baseband Architecture For Software Defined Radio

M. A. Fodha, H. Benfradj, A. Ghazel
2016 Zenodo  
This paper is a survey of recent works that proposes a baseband processor architecture for software defined radio. A classification of different approaches is proposed.  ...  The performance of each architecture is also discussed in order to clarify the suitable approaches that meet software-defined radio constraints.  ...  Reconfigurable hardware architecture for modulation [27] is implemented based on FPGA.  ... 
doi:10.5281/zenodo.1126159 fatcat:mdhjmvmfafdarg7m6uezpuxiei

Comparison of parallelization strategies for min-sum decoding of irregular LDPC codes

Hua Xu, Wei Wan, Wei Wang, Jun Wang, Jiadong Yang, Yun Wen
2013 Tsinghua Science and Technology  
The first implements min-sum LDPC decoders on multicore platforms using OpenMP, while the other uses the Compute Unified Device Architecture (CUDA) to parallelize LDPC decoding on Graphics Processing Units  ...  LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years.  ...  This study evaluated whether LDPC decoders can be implemented on general-purpose multicore architectures using two efficient parallel MSAs for LDPC decoding.  ... 
doi:10.1109/tst.2013.6678903 fatcat:ags3raehhjgyhmbwrik34vgh24

Implementation of a Burst Error and Burst Erasure Channel Emulator Using an FPGA Architecture

Caterina Travan, Francesca Vatta, Fulvio Babich
2020 Journal of Communications Software and Systems  
The implementation can be easily extended to other FPGA architectures.  ...  In this paper, the hardware implementation of a burst error channel and a burst erasure channel simulator in Cyclone II Field Programmable Gate Array (FPGA) is proposed.  ...  hardware, namely, a multicore CPU, a general purpose GPU, or an FPGA.  ... 
doi:10.24138/jcomss.v16i1.766 fatcat:6wjdrtcsfff5vkyvo6lcgqnhx4

CELLA: FPGA Based Candidate Execution with Low Latency Approach for Soft MIMO Detector

Erulappan Sakthivel, Kasinathan Pounraj, Veluchamy Malathi, Muruganantham Arunraja, Govindaraj Perumalvignnesh
2016 Circuits and Systems  
In order to attain both BER and FPGA level performance in a single system, CELLA is developed in this work.  ...  The intention of this work is to observe the performance of Candidate Execution with Low Latency Approach for soft MIMO detector in FPGA (CELLA).  ...  This is not included here to minimize the ED distance metrics. The experimental results of the proposed system are implemented in Xilinx Virtex 5 XC5VSX240T platform.  ... 
doi:10.4236/cs.2016.78152 fatcat:b4ixu2ly3beg5eh4qmu6jxl2gy

Software-defined Radios: Architecture, State-of-the-art, and Challenges [article]

Rami Akeela, Behnam Dezfouli
2018 arXiv   pre-print
In addition, we highlight key contrasts between SDR architectures with regards to energy, computing power, and area, based on a set of metrics.  ...  Consequently, SDR has earned a lot of attention and is of great significance to both academia and industry.  ...  Finally, authors in [110] compare GPPs, GPUs, and FPGAs through the implementation of LDPC decoders, and their results lead to the conclusion that GPUs and FPGAs perform better than GPPs.  ... 
arXiv:1804.06564v1 fatcat:ogkut4aibnfarbrvjkihdfiqnu

LDPC Decoding on GPU for Mobile Device

Yiqin Lu, Weiyue Su, Jiancheng Qin
2016 Mobile Information Systems  
To realize efficient software LDPC decoding on the mobile device, the LDPC decoding feature on communication baseband chip should be replaced to save the cost and make it easier to upgrade decoder to be  ...  By dividing the check matrix into several parts to make full use of both the local memory and private memory on GPU and properly modify the code capacity each time, our implementation on a mobile phone  ...  There are a large number of studies using FPGA to realize the efficient LDCP decoder [3, 4] .  ... 
doi:10.1155/2016/7048482 fatcat:bo4qrh2urngqzpyofjlcnrzvwq

Hardware-Based Linear Program Decoding with the Alternating Direction Method of Multipliers [article]

Mitchell Wasson, Mario Milicevic, Stark C. Draper, Glenn Gulak
2016 arXiv   pre-print
This implementation targets a Field-Programmable Gate Array (FPGA) platform to evaluate error-rate performance and estimate resource usage.  ...  However, LP decoding, when implemented with general solvers, does not scale to large blocklengths and is not suitable for a parallelized implementation in hardware.  ...  Figure 4 presents an overview of our partially-parallel QC-LDPC decoder architecture for the special case of a (3, 6)-regular QC-LPDC code.  ... 
arXiv:1611.05975v1 fatcat:bl6bbnsan5fv7i5obx3ro7vnii

Exploring manycore architectures for next-generation HPC systems through the MANGO approach

José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragić, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella (+22 others)
2018 Microprocessors and microsystems  
Acknowledgements This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 671668.  ...  Phase 2 -From FPGA stand-alone board to a dedicated chassis.  ...  most from a hardware implementation of from acceleration.  ... 
doi:10.1016/j.micpro.2018.05.011 fatcat:gf4jczkxgzcpfdbgqygmwbkwfq

Implementation Of Decoders for LDPC Block Codes and LDPC Convolutional Codes Based on GPUs [article]

Yue Zhao, Francis C. M. Lau
2012 arXiv   pre-print
The LDPCCC is derived from a pre-designed quasi-cyclic LDPC block code with good error performance.  ...  In our proposed decoder architecture, Γ (a multiple of a warp) codewords are decoded together and hence the messages of Γ codewords are also processed together.  ...  We also develop a GPU-based decoder for the LDPC convolutional codes. We propose a decoder architecture for LDPCCC derived from QC-LDPC block-code.  ... 
arXiv:1204.0334v2 fatcat:srn5pnh7ajhsddtolgoxbnvg3e

Enabling development of OpenCL applications on FPGA platforms

Kavya Shagrithaya, Krzysztof Kepa, Peter Athanas
2013 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors  
Whether used to augment a processor or as a stand-alone device, these reconfigurable architectures are being deployed in a large number of implementations owing to the massive amounts of parallelism offered  ...  In this thesis, a compilation flow to generate customized application-specific hardware descriptions from OpenCL computation kernels is presented.  ...  These range from Graphic Processing Units (GPU), Field Programmable Gate Arrays (FPGA), heterogeneous multicore processors like Cell to hybrid architectures like Convey HC-1.  ... 
doi:10.1109/asap.2013.6567546 dblp:conf/asap/ShagrithayaKA13 fatcat:5cb6mpbe35htjax7vn5skzbrwa

Data Parallelism for Belief Propagation in Factor Graphs

Nam Ma, Yinglong Xia, Viktor K. Prasanna
2011 2011 23rd International Symposium on Computer Architecture and High Performance Computing  
We propose a complete belief propagation algorithm using the primitives to perform exact inference in factor graphs.  ...  We investigate data parallelism for belief propagation in acyclic factor graphs on multicore/manycore processors.  ...  Acknowledgements Thanks to the management, staff, and facilities of the Intel Manycore Testing Lab ([1, 2]).  ... 
doi:10.1109/sbac-pad.2011.34 dblp:conf/sbac-pad/MaXP11 fatcat:ziclr2joovhn7jeczbpbyomumi
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