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Parallel and Pipelined Hardware Implementation of Radar Signal Processing for an FMCW Multi-channel Radar

Eugin Hyun
2015 Elektronika ir Elektrotechnika  
In order to effectively support the parallel and pipelined architecture, we propose a data-routing-schemed DBF and fine-grained DBF architecture.  ...  The results from implementation of the proposed hardware resources and processing times are also presented.  ...  II IMPLEMENTATION SUMMARY FOR THE PROPOSED SYSTEM WITH FINE-GRAINED PIPELINED AND PARALLEL DBF.TABLE III. TOTAL PROCESSING TIME FOR THE NEW ARCHITECTURE WITH FINE-GRAINED PIPELINED DBF.  ... 
doi:10.5755/j01.eee.21.2.7606 fatcat:qptsxuyuvvf23dpncu7ewlysie

Deterministic multi-core parallel routing for FPGAs

Marcel Gort, Jason H. Anderson
2010 2010 International Conference on Field-Programmable Technology  
In the fine-grained approach, the task of routing an individual load pin on a signal is parallelized using threads.  ...  In the coarse-grained approach, sets of design signals are assigned to different processor cores and routed concurrently.  ...  ACKNOWLEDGEMENTS The authors thank Scott Chin for suggesting that node expansion might be parallelized on a fine-grain level.  ... 
doi:10.1109/fpt.2010.5681758 dblp:conf/fpt/GortA10 fatcat:uw7lhwqu4na3vi2iiqjuik3rkm

FPGA on FPGA: Implementation of Fine-grained Parallel Genetic Algorithm on Field Programmable Gate Array

A. AL-Marakeby
2013 International Journal of Computer Applications  
Hybrid models are not the most common due to the need for additional new parameters to account for a more complex topology structure [7] . FINE-GRAINED PARALLEL GENTIC ALGORITHM.  ...  Master/Slave , Fine-grained , Coarse grained, and hybrid parallel genetic algorithms are the most common techniques used in parallelization of Genetic Algorithm [7 ] [ 11] .  ... 
doi:10.5120/13867-1725 fatcat:57gdqu4cb5gstfmvpzrvso35bm

Generating Fine-Grain Multithreaded Applications Using a Multigrain Approach

Jaime Arteaga, Stéphane Zuckerman, Guang R. Gao
2017 ACM Transactions on Architecture and Code Optimization (TACO)  
of fine-grain multithreaded applications from programs featuring OpenMP's API, allowing OpenMP programs to be run on top of a fine-grain event-driven program execution model.  ...  To evaluate the type of applications that benefit from executing in a unified fine-grain program execution model, this article presents a multigrain parallel programming environment for the generation  ...  Each codelet instance is assigned an ID from 0 to N − 1. Synchronization codelets may be instantiated only once or implemented as a tree to reduce signaling overhead.  ... 
doi:10.1145/3155288 fatcat:pqpz423lufdb5d7xycqscenssm

Parallel Implementation of GC-Based MPC Protocols in the Semi-Honest Setting [chapter]

Mauro Barni, Massimo Bernaschi, Riccardo Lazzeretti, Tommaso Pignata, Alessandro Sabellico
2014 Lecture Notes in Computer Science  
To analyze the efficiency of parallel implementation, a biometric scenario, having an intrinsically parallel nature, is considered.  ...  We propose two different types of parallelization: fine-grained, based on the parallel evaluation of gates, and coarse grained, based on the parallelization of macro-blocks.  ...  For both scenarios, we compare the sequential implementation to the parallel implementations (fine-grained, coarse grained and coarse-grained with fine-grained parallelization inside the blocks).  ... 
doi:10.1007/978-3-642-54568-9_5 fatcat:p3v6vaskhjdtnegpagcw5lnatq

Efficient Implementation On Multiprocessors : The Problem Of Signal Processing Applications Modelling

F. Boeri, L. Kwiatkowski, J-P. Stromboni
1996 Zenodo  
From the implementation of the application fined-grained modelling, the Gantt processing graph is studied.  ...  Implementation of the application fined-grained modelling requires a distribution of tasks to the parallel resources.  ... 
doi:10.5281/zenodo.35942 fatcat:obpsfz2w5bcc7c2xgi2nzudlrm

FPGA Implementation of On-Chip Network

N Murali Krishna
2018 DJ Journal of Advances in Electronics and Communication Engineering  
Coarse grained architecture is suggested due to its innumerable advantages over fine grained architecture.  ...  Coarse Grained Arrays (CGAs) with run-time re-configurability play a challenging task to design Network on-Chip (NoC) communication systems satisfying the power and area of embedded system.  ...  NI is used to convert the wishbone signals from the IP cores to packets. RESULTS AND DISCUSSION 32 bit UART RISC processor designed with dynamic power management is implemented on FPGA based NoC.  ... 
doi:10.18831/ fatcat:jfgj5g733zbi5mgkfypfzvn6ga

Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor

Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay S. Lee
1998 SIGARCH Computer Architecture News  
As this fine-grain parallelism is orthogonal to ILP and coarse threads, it complements both methods and provides an opportunity for greater speedup.  ...  With a three-processor implementation of the MAP, fine-grain speedups of 1.2-2.1 are demonstrated on a suite of applications.  ...  Thanks also to the Spectrum Design Services group at Cadence Design Systems for their contributions to the physical design of the MAP chip.  ... 
doi:10.1145/279361.279399 fatcat:neuvlxywjvfpfgpiuqostf5kci


Kishan Shivhare, Gaurav Bhardwaj
2016 International Journal of Advanced Research  
Data converters 1 and 2 convert 1-b image signals into 32-b parallel data of same format as the data from SDRAM and registers.  ...  Data converters 1 and 2 convert 1-b image signals into 32-b parallel data of same format as the data from SDRAM and registers.  ... 
doi:10.21474/ijar01/787 fatcat:sdngspuzuzd5tftpov52y332ja

Parallel performance of the fine-grain pipeline FPGA image processing system

M. Gorgoń
2012 Opto-Electronics Review  
It is proven that for a pipeline architecture implemented in FPGA, a linear speedup is achieved and parallel efficiency is equal to one.  ...  purpose processor, digital signal processor, graphical processing unit, application specific Integrated circuit and field programmable gate array.  ...  The possibility to implement finegrain parallelization in an FPGA allows for pipelined image processing [6, 12, 29, 38, 39] .  ... 
doi:10.2478/s11772-012-0021-2 fatcat:htp3q2oylreura3yrkmtfxl5mq

Spark-based parallel calculation of 3D fourier shell correlation for macromolecule structure local resolution estimation

Yongchun Lü, Xiangrui Zeng, Xinhui Tian, Xiao Shi, Hui Wang, Xiaohui Zheng, Xiaodong Liu, Xiaofang Zhao, Xin Gao, Min Xu
2020 BMC Bioinformatics  
In this paper, we proposed a K-V format based fine-grained 3D array partition method in Spark to parallel calculating 3D FSC for getting a 3D local resolution density map. 3D local resolution density map  ...  This paper proposes a new fine-grained 3D array partition method by key-value format in Spark. Our method first converts 3D images to key-value data (K-V).  ...  downloaded at https://www. Two half maps of SA of Sar1-Sec23-Sec24 (EMDB: EMD-0044) can be downloaded at EMD-0044 The source code of the Spark-based parallel  ... 
doi:10.1186/s12859-020-03680-6 pmid:32938398 pmcid:PMC7495889 fatcat:7vdrwo5ppfbetcb3slx3mh2nuu

Hardware Cost Analysis for Weakly Programmable Processor Arrays

Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jurgen Teich
2006 2006 International Symposium on System-on-Chip  
The inherent parallelism in these application fields has to be reflected at the hardware level to achieve high performance.  ...  Coarse-grained reconfigurable architectures support a high degree of parallelism at multiple levels.  ...  Existing fine-grained and coarse-grained architectures both lack programmability as a result of paradigms, which are very different from the von Neumann's.  ... 
doi:10.1109/issoc.2006.321996 dblp:conf/issoc/KisslerHKT06 fatcat:ira6n7n3qfac7ib5j7vd7gszgm

A prototypical self-optimizing package for parallel implementation of fast signal transforms

Kang Chen, J. R. Johnson
2002 Proceedings 16th International Parallel and Distributed Processing Symposium  
This paper presents a self-adapting parallel package for computing the Walsh-Hadamard transform (WHT), a prototypical fast signal transform, similar to the fast Fourier transform.  ...  Using a search over a space of mathematical formulas representing different algorithms to compute the WHT, the package finds the best parallel implementation on a given shared-memory multiprocessor.  ...  This problem does not occur for the fine-grained implementation of DDL.  ... 
doi:10.1109/ipdps.2002.1015545 dblp:conf/ipps/ChenJ02 fatcat:rh3q6envizf3jfgc4uv7csmygq

Fine-grain OpenMP runtime support with explicit communication hardware primitives

P Tendulkar, V Papaefstathiou, G Nikiforos, S Kavadias, D S Nikolopoulos, M Katevenis
2011 2011 Design, Automation & Test in Europe  
of fine-grain parallelism in OpenMP programs.  ...  We present a runtime system that uses the explicit on-chip communication mechanisms of the SARC multi-core architecture, to implement efficiently the OpenMP programming model and enable the exploitation  ...  The input sizes range from 128 to 4096 integer elements and produce extremely fine-grain parallel tasks. We use remote DMAs for the butterfly data exchange during bitonic merge.  ... 
doi:10.1109/date.2011.5763299 dblp:conf/date/TendulkarPNKNK11 fatcat:3jibghpy3vbtrnnjazo5kkifru

Implementing directed acyclic graphs with the heterogeneous system architecture

Sooraj Puthoor, Ashwin M. Aji, Shuai Che, Mayank Daga, Wei Wu, Bradford M. Beckmann, Gregory Rodgers
2016 Proceedings of the 9th Annual Workshop on General Purpose Processing using Graphics Processing Unit - GPGPU '16  
Asynchronous dependency-driven tasking is one such programming model that allows the computation to be expressed as a directed acyclic graph (DAG) and exposes fine-grain task management to the programmer  ...  In this paper, we demonstrate that the Heterogeneous System Architecture (HSA) exposes the above capabilities, and we validate their benefits by implementing three well-referenced applications using fine-grain  ...  However, the parallelization opportunity in NW comes from the ability to exploit more fine-grain parallelism when there is not enough tiles in a strip to fill the GPU.  ... 
doi:10.1145/2884045.2884052 dblp:conf/ppopp/PuthoorACDWBR16 fatcat:mkekkvzr2zbhdfftehp6ztdcci
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