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Using Rtos In The Aaa Methodology Automatic Executive Generation

O. Deforges, Jean Franois Nezan, Mickael Raulet, Ghislain Roquier
2006 Zenodo  
To this end, we developed new libraries to specify the translation of macro-intructions. Figure 3 describe the two approaches from software description to hardware implementation.  ...  Notice, in both cases, real-time distributed executives are statics, the deterministic behaviour of the real-time execution is guaranteed off-line by the distribution scheduling heuristic. 2 Synchronized  ... 
doi:10.5281/zenodo.39917 fatcat:a5wcm3qcwzdojimyx7lwkvhd4y

Two novel cache management mechanisms on CPU-GPU heterogeneous processors

Huijing Yang, Tingwen Yu
2021 Research Briefs on Information & Communication Technology Evolution  
DGMA scheme monitors GPU's cache performance metrics at run time and set appropriate threshold to dynamically change the cache ratio of the mutual LLC between various kernels.  ...  To alleviate the unfair contention within CPUs and GPUs for the cache capability, we propose two novel cache supervision mechanisms: static cache partitioning scheme based on adaptive replacement policy  ...  The authors would like to thank the reviewers for their efforts and for providing helpful suggestions that have led to several important improvements in our work.  ... 
doi:10.22667/rebicte.2021.06.15.001 doaj:894b43889d8f4f608eff843bea80cdc3 fatcat:6xc6imq3kjgsfak66tq5wvykhy

Introducing control-flow inclusion to support pipelining in custom instruction set extensions

Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel Topham, Paolo Ienne
2009 2009 IEEE 7th Symposium on Application Specific Processors  
To address this concern, we introduce a new type of ISE that borrows ideas from zero-overhead loop instructions to permit pipelined execution of loops.  ...  Often, there are intermittent calls to branch instructions, at a minimum, that prevent the pipelined execution of subsequent calls to the same ISE within a loop.  ...  have parallel functional units and require static scheduling at compile-time.  ... 
doi:10.1109/sasp.2009.5226328 dblp:conf/sasp/ZuluagaKBTI09 fatcat:a3vola3qvzd45ljm2jobnrelj4

Combining compiler and runtime IPC predictions to reduce energy in next generation architectures

Saurabh Chheda, Osman Unsal, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
2004 Proceedings of the first conference on computing frontiers on Computing frontiers - CF'04  
Overall, static IPC based resource throttling alone can save up to 14% energy in the processor with less than 5% IPC degradation.  ...  program ILP burstiness and helps meet applications' target performance: an important criterion in the real-time domain.  ...  Intuitively, if the instruction window is large enough, intructions across loop iterations could be scheduled out-of-order creating an effect that is similar to software pipelining, which is not yet captured  ... 
doi:10.1145/977091.977125 dblp:conf/cf/ChhedaUKKM04 fatcat:uvtrfe22hfe6pkkjg5tmzgtuiq

Very Long Instruction Word architectures and the ELI-512

Joseph A. Fisher
1983 Proceedings of the 10th annual international symposium on Computer architecture - ISCA '83  
sequential machine --we expect 10 to 30 times faster.  ...  In Very Long Instruction Word machines, many statically scheduled, tightly coupled, fine-grained operations execute in parallel within a single instruction stream.  ...  ACKNOWLEDGEMENTS Invaluable contributions to the ELI design and the Bulldog Partly to reduce the scope of the project and partly because of the the nature of VLIWs, we are limiting ourselves in various  ... 
doi:10.1145/800046.801649 dblp:conf/isca/Fisher83 fatcat:55vmbcfodvdu3pmfm5bbg3q2k4

Timed Games for Computing Worst-Case Execution-Times [article]

Franck Cassez
2010 arXiv   pre-print
of timed automata modeling the architecture; and 3) compute the WCET as the optimal time to reach a winning state in this game.  ...  We also show that this framework can easily be extended to take into account dynamic changes in the speed of the processor during program execution. %  ...  The author would like to thank Bernard Blackham (NICTA, Sydney) and Gernot Heiser (NICTA, Sydney) for their helpful comments and support.  ... 
arXiv:1006.1951v1 fatcat:76ajlckcendlli2oh62wa4jb3m

STARPro — A new multithreaded direct execution platform for Esterel

Simon Yuan, Sidharta Andalam, Li Hsien Yoong, Partha S. Roop, Zoran Salcic
2009 Electronical Notes in Theoretical Computer Science  
Esterel programs have traditionally been compiled to software code for general purpose processors or to hardware netlists.  ...  While such powerful features make it intuitive to write specifications in Esterel, its compilation and efficient execution has been non-trivial.  ...  Acknowledgement The authors would like to acknowledge the assistance of Rohan Aggrawal in STARPro's implementation, and Chia-Hao Chou for his contribution to the design.  ... 
doi:10.1016/j.entcs.2008.01.005 fatcat:nv34m2aabzba3eer3fm5xamywu

The proposed level-3 trigger system for STAR

C. Adler, J. Berger, M. Demello, D. Flierl, J. Landgraf, J.S. Lange, M.J. LeVine, V. Lindenstruth, A. Ljubicic, J. Nelson, D. Roehrich, E. Schafer (+6 others)
2000 IEEE Transactions on Nuclear Science  
The level-3 trigger system of the STAR experiment will in the final stage consist of a farm of 24 ALPHA/Linux processors, interconnected by SCI (Scalable Coherent Interface).  ...  The track data will be transfered to a global level-3 CPU (expected data transfer rate ³48 MB/s), performing online event analysis tasks (e.g. invariant mass reconstruction) with a design trigger input  ...  The ALPHA chip is statically scheduled, i.e. the performance depends on the sequence of instructions.  ... 
doi:10.1109/23.846181 fatcat:zmkmuhzuqfhfrbtfjcbcwnzkh4

Design Automation Model for Application-Specific Processors on Reconfigurable Fabric [chapter]

Arda Yurdakul, Roza Ghamari, Bayram Kurumahmut, Gokhan Kabukcu
2010 Lecture Notes in Electrical Engineering  
In this paper, we propose a new model for automated design of application-specific processors in run-time reconfigurable architectures, solving the aforementioned inefficiency problems.  ...  The process of embedded system design on reconfigurable architectures needs smart solutions to reduce development life-cycle and to use resources efficiently at run-time.  ...  which is assumed to be static during runtime.  ... 
doi:10.1007/978-90-481-9304-2_7 fatcat:4tu57rcsand27dqf4kxjg2gdqm

Saburo, a tool for I/O and concurrency management in servers

G. Loyaute, R. Forax, G. Roussel
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
The aim of our development tool is to improve programmer productivity and portability, decreasing development time, and reducing bugs or deadlock problems.  ...  This architecture also permits to extend very easily an application, adding vertices and edges to the graph.  ...  NEST [18] is a specification language approach close to Lex and Yacc allowing to generate the server code automatically from a grammatical description of the protocol.  ... 
doi:10.1109/ipdps.2006.1639508 dblp:conf/ipps/cFR06 fatcat:5nushfaowvabjixukz2oqikrhq

Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns [article]

Hasan Hassan
2016 arXiv   pre-print
If a later DRAM request hits in that table, the memory controller uses lower timing parameters, leading to reduced DRAM latency.  ...  Row addresses are removed from the table after a specified duration to ensure rows that have leaked too much charge are not accessed with lower latency.  ...  Then the scheduling logic decides which request from the request buffer to serve first.  ... 
arXiv:1609.07234v1 fatcat:5iuox7vjmndu3dciwbvlzpc5hu

Skiing the embedded systems mountain

Ingrid Verbauwhede, Patrick Schaumont
2005 ACM Transactions on Embedded Computing Systems  
In an embedded context, where these are very tightly connected, this leads to large inefficiencies both in design time and design results.  ...  A horizontal exploration axis covers various architecture alternatives including application-specific integrated circuits (ASIC), domain-specific processors, digital signal processors (DSP), embedded cores  ...  In contrast to previous blocks, where all operations can be scheduled statically (and optimized using static-scheduling principles), the students • I. Verbauwhede and P.  ... 
doi:10.1145/1086519.1086523 fatcat:rwhmgyzw5bgk3kr7fch7cmtd6y

Finding schedule-sensitive branches

Jeff Huang, Lawrence Rauchwerger
2015 Proceedings of the 2015 10th Joint Meeting on Foundations of Software Engineering - ESEC/FSE 2015  
This paper presents an automated, precise technique, TAME, for identifying schedule-sensitive branches (SSBs) in concurrent programs, i.e., branches whose decision may vary depending on the actual scheduling  ...  of traces to analyse, yet without sacrificing precision.  ...  The online tracing time ranges from a few milliseconds to 2s.  ... 
doi:10.1145/2786805.2786840 dblp:conf/sigsoft/HuangR15 fatcat:sf7uz5jfnvfcrmo4rtyhny5vzq

Processor design based on dataflow concurrency

Sotirios G. Ziavras
2003 Microprocessors and microsystems  
to execute or when all their operand(s) are to be available within a few clock cycles.  ...  This approach results in outstanding performance and elimination of large numbers of redundant operations that plague current processor designs.  ...  Acknowledgment: The author would like to thank Mr. S.N. Kopec for the VHDL implementation of the PIM used in the proposed design.  ... 
doi:10.1016/s0141-9331(03)00021-8 fatcat:azqz3om2mvdsddmhas6ujlo6ue

Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking

Brian Greskamp, Josep Torrellas
2007 Parallel Architecture and Compilation Techniques (PACT), Proceedings of the International Conference on  
Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness.  ...  To recover some of the lost performance and improve single-thread performance, this paper presents the Paceline leader-checker microarchitecture.  ...  At the same time, the High-Reliability design provides tolerance to transient faults such as soft errors.  ... 
doi:10.1109/pact.2007.4336213 fatcat:gjubq23buzgxnljrveoywhge44
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