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Towards Design Verification and Validation at Multiple Levels of Abstraction [chapter]

Holger Giese, Martin Kardos, Ulrich Nickel
2002 IFIP Advances in Information and Communication Technology  
We will further explain how the use of multiple Abstract State Machine meta-models permits simulation and model checking at different levels of abstraction  ...  The ISILEIT project aims at the development of a seamless methodology for the integrated design. analysis and validation of such embedded systems.  ...  The presented support for multiple levels of abstractions by means of different ASM meta-models enables the validation and verification during the ongoing design.  ... 
doi:10.1007/978-0-387-35599-3_8 fatcat:h6rk6bsz55hvbgdz4vekm5tumu

SFB/TR 14 AVACS – Automatic Verification and Analysis of Complex Systems (Der Sonderforschungsbereich/Transregio 14 AVACS – Automatische Verifikation und Analyse komplexer Systeme)

Bernd Becker, Andreas Podelski, Werner Damm, Martin Fränzle, Ernst-Rüdiger Olderog, Reinhard Wilhelm
2007 it - Information Technology  
analysis of complex systems.  ...  A particular focus of the project is on models of complex transportation systems and their safety requirements.  ...  The analysis and verification of real-time systems is based on computational models of such systems. These models describe different levels of abstraction in the development process.  ... 
doi:10.1524/itit.2007.49.2.118 fatcat:2mb2uwdoazcirmt7ghfq3p7aua

Application Of Formal Methods For Designing A Separation Kernel For Embedded Systems

Kei Kawamorita, Ryouta Kasahara, Yuuki Mochizuki, Kenichiro Noguchi
2010 Zenodo  
A separation-kernel-based operating system (OS) has been designed for use in secure embedded systems by applying formal methods to the design of the separation-kernel part.  ...  Developing and testing of a prototype embedded application, a point-of-sale application, on the prototype OS demonstrated that the proposed architecture and the use of formal methods to design its kernel  ...  FORMAL DESIGN WITH B METHOD As mentioned above, one of the requirements defined by the Common Criteria for Information Technology Security Evaluation [5] for secure systems is formal design at the highest  ... 
doi:10.5281/zenodo.1071246 fatcat:6mm2w4dmwrgjbncpdqcfjobdcm

A Short Historical Survey of Functional Hardware Languages

Gang Chen
2012 ISRN Electronics  
This short historical survey is about functional languages specifically created for hardware design and verification.  ...  Functional programming languages offer a high degree of abstractions and clean semantics, which are desirable for hardware descriptions.  ...  FHLs may differ at the levels of abstraction: system level (e.g., Glass), architecture level (e.g., Hawk), algorithmic level (e.g., Bluespec), RTL level (e.g., Lava), netlist level (e.g., Wire), and layout  ... 
doi:10.5402/2012/271836 fatcat:n2iml6tnnzhzbcjyuslsmdpy64

New Aspects in HDL's Performance Evaluation

B. Andelkovic, V. Litovski, V. Zerbe
2005 EUROCON 2005 - The International Conference on "Computer as a Tool"  
New aspects in Hardware Description Language's (HDL) performance evaluation such as objectorientation, system-level modeling, analog and mixed-signal modeling, software description and verification capabilities  ...  Features of mainstream HDLs and verification languages VHDL-AMS, Java, SystemC, AleC++, MLDesigner, OpenVera, the e language, PSL and SystemVerilog are compared in the context of these aspects.  ...  It enables full-chip mixed-signal simulation at different levels of abstraction together with embedded software modules.  ... 
doi:10.1109/eurcon.2005.1629974 fatcat:urttnk375ze5fj5aooznv5aam4

Applied Assertion-Based Verification: An Industry Perspective

Harry Foster
2007 Foundations and Trends® in Electronic Design Automation  
However, today's assertion language standards lack the proper formalism necessary to express properties at all of the levels of abstraction illustrated in Figure 1. 2.  ...  Thus, Assertion Stakeholders Assertions added at any level of hierarchy (or abstractions) clearly benefit verification by reducing debugging time while clarifying design intent.  ... 
doi:10.1561/1000000013 fatcat:6krg4p273fdldoshnx5d7u3n2i

Unified Property Specification for Hardware/Software Co-Verification

Fei Xie, Huaiyu Liu
2007 Computer Software and Applications Conference (COMPSAC) Proceedings of the IEEE International  
Case studies have shown that xPSL is very effective in enabling co-verification of system-level properties and facilitating compositional reasoning.  ...  applied in co-verification to specify properties of hardware and software components, and furthermore entire embedded systems.  ...  of the components in system-level verification and can be reused across multiple systems if the components are reused.  ... 
doi:10.1109/compsac.2007.231 dblp:conf/compsac/XieL07 fatcat:yytxcy22vrbzpaepr3b7vrufae

Embedded Tutorials

2015 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems  
Tutorial II Abstract Formal Methods advanced to an important core technology in Computer-Aided Design (CAD).  ...  Capacity and speed go along with Moores Law, all the devices of a design, number of which is doubling every 18 months, must be handled by EDA software at acceptable speed. xvi xvi xiv xvii xvii Embedded  ...  Transaction modelling (TLM) is a new level of abstraction for creating and verifying a design.  ... 
doi:10.1109/ddecs.2015.68 fatcat:crbeu33dmvhjboq76sm6oiodq4

Verification of electronic systems

Alberto L. Sangiovanni-Vincentelli, Patrick C. McGeer, Alexander Saldanha
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
Formalization at the system level is crucial for real advances in verification.  ...  Decomposition Decomposition is the process of breaking up a system design into components described at the same level of abstraction.  ... 
doi:10.1145/240518.240539 dblp:conf/dac/Sangiovanni-VincentelliMS96 fatcat:52fgmr2625ebvfemmbmaizxzbu

Quantitative evaluation in embedded system design

Joost-Pieter Katoen
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
The evaluation of extra-functional properties of embedded systems, such as reliability, timeliness, and energy consumption, as well as dealing with uncertainty, e.g., in the timing of events, is getting  ...  We survey some main developments and trends in the modeling, and the analysis of these aspects and stress the importance of approaches that tackle both extrafunctional, as well as correctness aspects.  ...  Typically, embedded systems do not terminate and interaction usually takes place with multiple concurrent processes at the same time.  ... 
doi:10.1145/1403375.1403398 fatcat:ts74r2e2hneqjbruqoldevkv6a

The challenge of interoperability

Huafeng Yu, Prachi Joshi, Jean-Pierre Talpin, Sandeep Shukla, Shinichi Shiraishi
2015 Proceedings of the 52nd Annual Design Automation Conference on - DAC '15  
A novel model-based formal integration framework is being developed to enable architecture modeling, timing specification, formal semantics, design by contract and optimization in the system-level design  ...  timing relationship language, a formal contract language to express component-level requirements and validation of component integration, and the resulting high assurance system delivery.  ...  We adopt formal specification in an early stage of design at the modeling level.  ... 
doi:10.1145/2744769.2747945 dblp:conf/dac/YuJTSS15 fatcat:dlsu7o7t4bgebgx7bv4wrlk7z4

Systematic Model-in-the-Loop Test of Embedded Control Systems [chapter]

Alexander Krupp, Wolfgang Müller
2009 IFIP Advances in Information and Communication Technology  
This article addresses several shortcomings of embedded system verification.  ...  Current model-based development processes offer new opportunities for verification automation, e.g., in automotive development. The duty of functional verification is the detection of design flaws.  ...  The increasing demand for verification at an early abstraction level, like system level, has led to the creation and introduction of methods and languages for functional verification.  ... 
doi:10.1007/978-3-642-04284-3_16 fatcat:gumdgo7itvfnlbyikiw6yuu5wa

ESIDE: An Integrated Development Environment for Component-Based Embedded Systems

Nicholas T. Pilkington, Juncao Li, Fei Xie
2009 2009 33rd Annual IEEE International Computer Software and Applications Conference  
In this paper we present ESIDE, an integrated development environment for component-based embedded systems.  ...  We first describe the architecture and features of ESIDE. We then discuss several design decisions that we faced in developing ESIDE and the trade-offs in making these decisions.  ...  The time and memory usages are listed for verification of the system-level property on abstractions constructed from properties of the first-level components [10] .  ... 
doi:10.1109/compsac.2009.48 dblp:conf/compsac/PilkingtonLX09 fatcat:ygyvqxna5bd5dhl4vniiw7ueva

A formal experiment to assess the efficacy of certification standards [article]

Virginie Wiels
2014 arXiv   pre-print
Proving the efficacy of certification standards  ...  There are no complaints on errors that would be detected at abstract level (by the certification process) and that would not be an effective problem at the concrete level.  ...  As the correction of an embedded software cannot be verified, DO-178 defines an abstraction: the verification of correction is abstracted by the verification of objectives on HLR, LLR, software architecture  ... 
arXiv:1404.7542v1 fatcat:3356uot2brewzgw76v6v4iqtrm

An Overview of Methodologies and Tools in the Field of System-Level Design [chapter]

Vladimir D. Zivković, Paul Lieverse
2002 Lecture Notes in Computer Science  
We conclude that there still is a lot of room for research on the design of embedded systems-on-achip, especially in the areas of mixed-level simulation, verification, and synthesis.  ...  In this paper we present an overview of system level design methodologies and tools. Eight tools and their underlying methodologies are analysed.  ...  , e.g., support for synthesis, multiple abstraction levels, and formal analysis and verification.  ... 
doi:10.1007/3-540-45874-3_5 fatcat:loqef3axinglhe74v4o6yrlkfu
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