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Formal Verification of a Power Controller Using the Real-Time Model Checker UPPAAL

Klaus Havelund, Kim G. Larsen, Arne Skou
1999 BRICS Report Series  
A real-time system for power-down control in audio/video components<br />is modeled and verified using the real-time model checker UPPAAL.  ...  Hence, a component system is a multitasking system with hard real-time requirements, and we present techniques for modeling time consumption in such a multitasked,<br />prioritized system.  ...  Acknowledgments The B&O representative was Johnny Kudahl, who we thank for being extremely collaborative and productive, as well during the model building as in formulating the properties to be verified  ... 
doi:10.7146/brics.v6i8.20065 fatcat:rr4t7rbn45b2nlm6vkira545ca

Formal Verification of a Power Controller Using the Real-Time Model Checker Uppaal [chapter]

Klaus Havelund, Kim Guldstrand Larsen, Arne Skou
1999 Lecture Notes in Computer Science  
A real-time system for power-down control in audio/video components is modeled and verified using the real-time model checker UPPAAL.  ...  Hence, a component system is a multitasking system with hard real-time requirements, and we present techniques for modeling time consumption in such a multitasked, prioritized system.  ...  Acknowledgments The B&O representative was Johnny Kudahl, who we thank for being extremely collaborative and productive, as well during the model building as in formulating the properties to be verified  ... 
doi:10.1007/3-540-48778-6_17 fatcat:ry6peeklqbarphieer3ihayt74

HighSpec

J. S. Dong, P. Hao, X. Zhang, S. C. Qin
2006 Proceeding of the 28th international conference on Software engineering - ICSE '06  
HighSpec supports editing, type-checking as well as projecting OZTA models into TA models and Alloy Models so that TA model checkers-UPPAAL and the Alloy Analyzer can be utilized for verification.  ...  models for complex real-time systems.  ...  Acknowledgements We would like to thank Chen Qian, and He Kang for their part of work on the coding of HighSpec.  ... 
doi:10.1145/1134285.1134409 dblp:conf/icse/DongHZQ06 fatcat:gq3xteaqo5ex7jfd4ablfvdiiu

Model-based system analysis using Chi and Uppaal: An industrial case study

N.C.W.M. Braspenning, E.M. Bortnik, J.M. van de Mortel-Fronczak, J.E. Rooda
2008 Computers in industry (Print)  
Uppaal model checker  ...  The combination of models and realizations is then used for early analysis of the integrated system by means of validation, verification, and testing.  ...  Finally, the use of formal models enables the application of powerful model-based analysis techniques, like simulation and verification.  ... 
doi:10.1016/j.compind.2007.06.002 fatcat:4hd34lnw5jdkrlse536xy3ge4i

Formal design of communication checkers for ICCP using UPPAAL

Salman Malik, Robin Berthier, Rakesh B. Bobba, Roy H. Campbell, William H. Sanders
2013 2013 IEEE International Conference on Smart Grid Communications (SmartGridComm)  
We discuss use of UPPAAL in formal modeling of portions of ICCP.  ...  We discuss insights we gained and lessons we learned when modeling the protocol functionalities and running the UPPAAL model checker to prove critical security and safety properties, and we discuss the  ...  Revised formal model of an attacker in UPPAAL exploring a different set of denial-of-service vulnerabilities.Fig. 10. Initial formal model of a checker in UPPAAL.  ... 
doi:10.1109/smartgridcomm.2013.6688005 dblp:conf/smartgridcomm/MalikBBCS13 fatcat:t2pjfb5j4vaafouefjy5fwqaqa

Guest editors' introduction: Model checking in a nutshell

Holger Hermanns, Joost-Pieter Katoen
2002 The Journal of Logic and Algebraic Programming  
Given a model of the system (the "possible behavior") and a specification of the property to be considered (the "desirable behavior"), a model checker systematically checks the validity of the property  ...  Model checking Formal verification techniques try to answer questions related to the functional correctness of systems.  ...  It was a pleasure for us to prepare this issue, and we hope you will enjoy reading it!  ... 
doi:10.1016/s1567-8326(02)00030-9 fatcat:wdgjyg4gb5cehpanebma6kolke

Formal Verification of Device Discovery Mechanism using UPPAAL

Shivangi Arry, Amardeep Kaur
2012 International Journal of Computer Applications  
Using the verification tool UPPAAL a Bluetooth ad hoc system is modeled to formally verify the device discovery mechanism.  ...  Formal verification is one of the technique used to validate and verify the correctness of any protocol.  ...  There are three types of Formal verification techniques [3] : UPPAAL UPPAAL is a formal verification tool for modeling, simulation, and verification of real time system.  ... 
doi:10.5120/9392-3816 fatcat:me4fuxvuhbao5b5fyd4zhchlwy

Formal Verification and Design of Smart Stick for Blind People

Ayesha Naveed
2020 Zenodo  
This embedded system design has been verified using model checking and formal verification.  ...  Researchers these days widely use formal verification to verify software and embedded systems. This paper is based on a smart stick (embedded system) designed for blind people.  ...  For design verification UPPAAL model checker [3] is used. It can verify systems in real time by modeling them as networks in timed automata i.e. automation based on set of clocks.  ... 
doi:10.5281/zenodo.5148252 fatcat:24nvp3islzdwjhkkim7xvgieqe

Specification and verification of trustworthy component-based real-time reactive systems

Vasu Alagar, Mubarak Mohammad
2007 Proceedings of the 2007 conference on Specification and verification of component-based systems 6th Joint Meeting of the European Conference on Software Engineering and the ACM SIGSOFT Symposium on the Foundations of Software Engineering - SAVCBS '07  
This paper presents a formal methodology for the development of trustworthy real-time reactive systems (RTRS).  ...  The paper presents an overview of a component-based modeling that involves formal descriptions for trustworthy components.  ...  UPPAAL UPPAAL [4] is a mature model checker that has been used successfully for more than a decade to model check several types of concurrent real time systems.  ... 
doi:10.1145/1292316.1292327 dblp:conf/sigsoft/AlagarM07 fatcat:vqs2efbvkjfbnaeot2kr7pckfq

Formal verification considering a systematic modeling approach for function blocks

José Machado, Joel Galvão, Alexandre Fernandes
2017 Journal of the Brazilian Society of Mechanical Sciences and Engineering  
Timed Automata model for formal verification purposes, by model-checking, using UPPAAL model-checker.  ...  Formal verification of automation systems controller software is a complex task.  ...  Acknowledgements The authors are grateful to MEtRICs Research Centre for their support to this project.  ... 
doi:10.1007/s40430-017-0893-7 fatcat:bqkdktgl5vdgpfybep7r6zd6ue

Modeling and Verifying Real-Time Properties of Reactive Systems

Fenglin Han, Peter Herrmann, Hien Le
2013 2013 18th International Conference on Engineering of Complex Computer Systems  
The RTESMs are translated to guards, clocks and invariants of Timed Automata which can be analyzed by means of the model checker UPPAAL.  ...  In this paper, we describe an extension of the SPACE formalism which allows to model and verify also real-time behavior.  ...  As missing real-time constraints are a major issue for the violation of safety properties, we consider this work as a suitable extension to our endeavor for the creation of safe embedded systems (see,  ... 
doi:10.1109/iceccs.2013.13 dblp:conf/iceccs/HanHL13 fatcat:e5hqbhbiznhtxop2snaqmbqax4

Overview of Control Algorithm Verification Methods in Power Electronics Systems

Paweł Szcześniak, Iwona Grobelna, Mateja Novak, Ulrik Nyman
2021 Energies  
The paper presents the existing verification methods for control algorithms in power electronics systems, including the application of model checking techniques.  ...  Here we show the recent advancements in verification and performance assessment of power electronics systems with the usage of formal methods.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/en14144360 fatcat:voixwpnm5ba2bciljim3hzouae

A Formal Analysis of the Web Services Atomic Transaction Protocol with UPPAAL [chapter]

Anders P. Ravn, Jiří Srba, Saleem Vighio
2010 Lecture Notes in Computer Science  
The protocol is modelled and verified using the model checker Uppaal.  ...  Our model is based on an already available formalization using the mathematical language TLA + where the protocol was verified using the model checker TLC.  ...  It provides a powerful C-like syntax for describing guards and updates on transitions. Uppaal allows also real time clocks. However, this feature is not used in the present model.  ... 
doi:10.1007/978-3-642-16558-0_47 fatcat:fgad2cgnufhbfgxpjwhxawgysi

A Survey on Formal Verification Approaches for Dependable Systems [article]

Fayhaa Hameedi Khlaif, Shawkat Sabah Khairullah
2022 arXiv   pre-print
Because of their benefits and importance in the building of complex digital systems, the employment of formal V&V methods has recently attracted a lot of attention.  ...  To detect these errors and eliminate their effects on the system, new error detection approaches must be innovated and used in the design of the digital system.  ...  UPPAAL model checking tool has been used in [30] for real-time system modeling, validation, and verification.  ... 
arXiv:2204.12913v1 fatcat:y7jyq2gdjrgyxjtyibuknintfq

Comparing model checkers for timed UML activity diagrams

Zamira Daw, Rance Cleaveland
2015 Science of Computer Programming  
The study assesses the performance of different model checking tools, and strategies for converting activity diagrams into the tools input notation, for a class of real time activity diagrams used in medical  ...  The performance of these model checkers are then compared using a suite of UML activity diagrams of varying complexity developed by us for this purpose.  ...  Acknowledgement The authors would like to thank Peter Fontana for his help with the PES tool.  ... 
doi:10.1016/j.scico.2015.05.008 fatcat:aiicirp7yzdz7jay546hc4wsaq
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