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Formal verification of a pipelined processor with new memory hierarchy using a commercial model checker

H. Nakamura, T. Arai, M. Fujita
2002 Pacific Rim International Symposium on Dependable Computing, 2002. Proceedings.  
To investigate their ability, Solidify is selected as the representative of them and applied to a verification of a new processor. The processor adopts new memory hierarchy and new instructions.  ...  Its instruction issue is pipelined and in-order. Our experiment reveals that Solidify can verify the processor but drastic abstraction is indispensable for successful verification.  ...  The new architecture is called SCI-MA (abbreviation of Software Controlled Integrated Memory Architecture), which introduces a new memory hierarchy.  ... 
doi:10.1109/prdc.2002.1185653 dblp:conf/prdc/NakamuraAF02 fatcat:jzk2zzgnrfdmrmdh5eygoc54ka

Integrating Formal Verification into an Advanced Computer Architecture Course

M.N. Velev
2005 IEEE Transactions on Education  
This paper presents a sequence of three projects on design and formal verification of pipelined and superscalar processors: 1) a single-issue, five-stage DLX (an academic processor used widely for teaching  ...  The processors were designed and formally verified with a tool flow that was used to formally verify the M CORE processor at Motorola and detected bugs.  ...  A step included the extension of a pipelined processor from a previous step or from an earlier project with a new instruction type or a new mechanism.  ... 
doi:10.1109/te.2004.832880 fatcat:h7xexwcztbgp5gxjxr2ksfvjcy

Efficient formal verification of pipelined processors with instruction queues

Miroslav N. Velev
2004 Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04  
Presented is a method for formal verification of pipelined processors with long instruction queues.  ...  with 5 instruction-queue entries, but ran out of memory if the instruction queue was longer.  ...  Conclusions Presented was a method for efficient formal verification of pipelined processors with long instruction queues.  ... 
doi:10.1145/988952.988975 dblp:conf/glvlsi/Velev04 fatcat:lfgotr4qs5fo3aufubhpgzotxe

End-to-End Verification of Processors with ISA-Formal [chapter]

Alastair Reid, Rick Chen, Anastasios Deligiannis, David Gilday, David Hoyes, Will Keen, Ashan Pathirane, Owen Shepherd, Peter Vrabel, Ali Zaidi
2016 Lecture Notes in Computer Science  
In all processors, this has found bugs that would have been hard for conventional simulation-based verification to find and ISA-Formal is now a key part of ARM's formal verification strategy.  ...  To the best of our knowledge, this is the most broadly applicable formal verification technique for verifying processor pipeline control in mainstream commercial use.  ...  The primary cost of implementing ISA-Formal on a new processor is the effort required to implement the pipeline follower and abstraction function on each processor.  ... 
doi:10.1007/978-3-319-41540-6_3 fatcat:jaht4ofh4ngblkks2sxs3pujnq

Scalable hybrid verification of complex microprocessors

Maher Mneimneh, Fadi Aloul, Chris Weaver, Saugata Chatterjee, Karem Sakallah, Todd Austin
2001 Proceedings of the 38th conference on Design automation - DAC '01  
We introduce a new verification methodology for modern microprocessors that uses a simple checker processor to validate the execution of a companion high-performance processor.  ...  This verification approach enables the practical deployment of formal methods without impacting overall performance.  ...  In most modern formal verification approaches for control logic, the quantifier-free logic of equality with uninterpreted functions (LEUF) [7] provides a convenient formalism for datapath and memory  ... 
doi:10.1145/378239.378265 dblp:conf/dac/MneimnehAWCSA01 fatcat:qp2cnhdprvdadnlmkvrwzkzkzq

Formal verification of pipelined processors [chapter]

Randal E. Bryant
1998 Lecture Notes in Computer Science  
Correspondence checking formally verifies that a pipelined microprocessor realizes the serial semantics of the instruction set model.  ...  By representing the circuit state symbolically with Ordered Binary Decision Diagrams (OBDDs), this correspondence checking can be performed directly on a logic-level representation of the circuit.  ...  As an alternative to simulation, a number of researchers have investigated using formal verification techniques to prove that a pipelined processor preserves the semantics of the instruction set model.  ... 
doi:10.1007/bfb0054160 fatcat:76wk4vt7ordj5b5pduemvggk2e

Model-Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification

Gianpiero Cabodi, Paolo Camurati, Fabrizio Finocchiaro, Danilo Vendraminetto
2019 Electronics  
Since modern processors are hard to verify with standard formal verification techniques, we present a methodology that shows how to transform a realistic model of a speculative and out-of-order processor  ...  Spectre and Meltdown attacks in modern microprocessors represent a new class of attacks that have been difficult to deal with.  ...  Formal Verification of Microprocessors with Out-of-Order Execution Processors have always represented a serious challenge for design verification tools.  ... 
doi:10.3390/electronics8091057 fatcat:qobprib4lregbdi6fboehguhb4

Integrating formal verification and high-level processor pipeline synthesis

Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien L. Lu
2011 2011 IEEE 9th Symposium on Application Specific Processors (SASP)  
This paper presents our effort in integrating fully automated formal verification with a high-level processor pipeline synthesis framework.  ...  The paper reports case studies of applying this integrated framework to synthesize and formally verify pipelined RISC and CISC processors.  ...  Clarke from School of Computer Science at Carnegie Mellon, Scott Robinson from Intel, and our colleagues in the Computer Architecture Lab at Carnegie Mellon for their interaction and feedback.  ... 
doi:10.1109/sasp.2011.5941073 dblp:conf/sasp/NurvitadhiHKL11 fatcat:xrnee2lta5eexexddvf5ndr2di

Microprocessor Verification Using Efficient Decision Procedures for a Logic of Equality with Uninterpreted Functions [chapter]

Randal E. Bryant, Steven German, Miroslav N. Velev
1999 Lecture Notes in Computer Science  
Formal techniques to verify that a processor implements its instruction set specification could yield more reliable results at a lower cost than the current simulation-based verification techniques used  ...  The logic of equality with uninterpreted functions (EUF) provides a means of abstracting the manipulation of data by a processor when verifying the correctness of its control logic.  ...  As an alternative to simulation, a number of researchers have investigated using formal verification techniques to prove that a pipelined processor preserves the semantics of the instruction set model.  ... 
doi:10.1007/3-540-48754-9_1 fatcat:wdtljlkrjnah7pbloi2gzgcsqe

TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories

Miroslav N. Velev, Randal E. Bryant
2005 International Journal of Embedded Systems  
We present a tool flow for high-level design and formal verification of embedded processors.  ...  An earlier version of our tool flow was used to formally verify a model of the M • CORE processor at Motorola, and detected bugs.  ...  Adding signal Flush-to allow completion of partially executed instructions in a pipelined or superscalar processor without fetching new instructions-can be viewed as design for formal verification.  ... 
doi:10.1504/ijes.2005.008815 fatcat:a7c2n3mtljdpbeujgwyhl2zq4i

Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description

Luka Charvat, Ale Smrcka, Toma Vojnar
2012 2012 13th International Workshop on Microprocessor Test and Verification (MTV)  
The paper proposes an automated approach with a formal basis designed for checking correspondence between an RTL implementation of a microprocessor and a description of its instruction set architecture  ...  Although the approach does not provide full formal verification, experiments with the approach confirm that due to a different way it explores the state space of the design under test, it can find bugs  ...  Therefore, a use of formal verification is desirable even if it is applied in a bounded way. Unfortunately, formal verification is not a common part of the current microprocessor design tool chains.  ... 
doi:10.1109/mtv.2012.19 dblp:conf/mtv/CharvatSV12 fatcat:tx5hiqdq3renjnp2o3diolxpdy

HADES: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems

Lukáš Charvát, Aleš Smrčka, Tomáš Vojnar
2016 Electronic Proceedings in Theoretical Computer Science  
HADES is a fully automated verification tool for pipeline-based microprocessors that aims at flaws caused by improperly handled data hazards.  ...  It focuses on single-pipeline microprocessors designed at the register transfer level (RTL) and deals with read-after-write, write-after-write, and write-after-read hazards.  ...  Experimental Evaluation We have tested HADES on five processors: TinyCPU is a small 8-bit processor, mainly used for testing new verification methods.  ... 
doi:10.4204/eptcs.233.9 fatcat:o6s5q5h3c5hujly63vxebyhlfq

Formal verification of an Intel XScale processor model with scoreboarding, specialized execution pipelines, and impress data-memory exceptions

S.K. Srinivasan, M.N. Velev
2003 First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.  
The XScale is a superpipelined RISC processor with 7-stage integer, 8-stage memory, and variable-latency multiply-and-accumulate execution pipelines.  ...  We present the formal verification of an Intel XScale processor model.  ...  Conclusion We formally verified a model of the Intel XScale superpipelined RISC processor where the main execution, enhanced memory, and MAC pipelines, have different latencies.  ... 
doi:10.1109/memcod.2003.1210090 dblp:conf/memocode/SrinivasanV03 fatcat:auj4ocrh2rbrfbp7ocvhmtigea

A methodology for validation of microprocessors using symbolic simulation

Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy Abadir
2005 International Journal of Embedded Systems  
A significant bottleneck in the validation of processors is the lack of a golden reference model.  ...  Thus, many existing approaches employ a bottom-up methodology by using a combination of simulation techniques and formal methods.  ...  We would like to acknowledge the members of the ACES laboratory for their inputs.  ... 
doi:10.1504/ijes.2005.008805 fatcat:dhd3uvfm2nbynihv4jtk2arss4

Formal verification of an ARM processor

V.A. Patankar, A. Jain, R.E. Bryant
1999 Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)  
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor.  ...  The verification was done concurrently with the design implementation of the processor. Our verification did uncover 4 bugs that were reported back to the designer in a timely manner.  ...  This weakness leads us to think about formal verification. Formal verification uses a set of languages, tools and techniques to mathematically reason about the hardware system.  ... 
doi:10.1109/icvd.1999.745161 dblp:conf/vlsid/PatankarJB99 fatcat:foods3aps5e2tgof46lqlym2cy
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