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Formal Verification of Peephole Optimizations in Asynchronous Circuits [chapter]

Xiaohua Kong, Radu Negulescu
Formal Techniques for Networked and Distributed Systems  
This paper proposes and applies novel techniques for formal verification of peephole optimizations in asynchronous circuits.  ...  We present the verification of speed-optimizations in an asynchronous arbiter as a case study.  ...  Peephole Optimizations in Asynchronous Circuits By peephole optimizations we mean local changes in circuit sub-modules that do not affect the rest of the circuit or the operation of the circuit as a whole  ... 
doi:10.1007/0-306-47003-9_14 fatcat:zk7wh65nbnbjrf73ifuwbcmqce

Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages

Jian Liu, Steven M. Nowick, Mingoo Seok
2013 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems  
OVERVIEW My main research is on asynchronous and mixed-timing digital design. Asynchronous circuits have no centralized or global clock.  ...  There is also a recent surge of interest in industry in hybrid designs, which connect standard synchronous components (e.g. processors, memories) through flexible asynchronous interconnection networks,  ...  Nowick, "Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems.''  ... 
doi:10.1109/async.2013.29 dblp:conf/async/LiuNS13 fatcat:pgi4on5mbffj3fylrygmhghspy

Asynchronous Design—Part 2: Systems and Methodologies

Steven M. Nowick, Montek Singh
2015 IEEE design & test  
Part 1 covered foundations of asynchronous design, and highlighted recent applications, including commercial advances and use in emerging application areas.  ...  Part 2 focuses on methodologies for designing asynchronous systems, including basics of hazards, synthesis and optimization methods for both logic-level and high-level synthesis, and the development of  ...  Acknowledgment The authors appreciate the funding support of the National Science Foundation under Grants CCF-1219013, CCF-0964606, and OCI-1127361.  ... 
doi:10.1109/mdat.2015.2413757 fatcat:bpxnljdkofh6ppyovk6sp4pknm

Logic decomposition of speed-independent circuits

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, A. Yakovlev
1999 Proceedings of the IEEE  
This paper presents a new method for logic decomposition of speed-independent circuits that solves the problem in two major steps: 1) logic decomposition of complex gates and 2) insertion of new signals  ...  Logic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits.  ...  His research interests include the synthesis of asynchronous and low-power circuits, the concurrent design of mixed hardware and software systems, and the formal verification of digital systems.  ... 
doi:10.1109/5.740027 fatcat:iip5auyd3jbexpfeu7y2ijfgem

Logic Synthesis of Handshake Components Using Structural Clustering Techniques [chapter]

Francisco Fernández-Nogueira, Josep Carmona
2009 Lecture Notes in Computer Science  
A methodology to optimize handshake circuits is presented. The approach selects clusters of the initial handshake network for which signals representing internal channels within a cluster are hidden.  ...  Experimental results in area and performance have been obtained to measure the optimization on typical Balsa examples.  ...  Logic synthesis achieves global optimizations that can improve in orders of magnitude the local (peephole) optimizations applied in asynchronous HDLs [9, 6] .  ... 
doi:10.1007/978-3-540-95948-9_19 fatcat:qeikwfp7lrhnllf72sw6w3hjme

Asynchronous design methodologies: an overview

S. Hauck
1995 Proceedings of the IEEE  
Thus, most portions of a circuit must be carefully optimized to achieve the highest clock rate, including rarely used portions of the system.  ...  In contrast, designers of asynchronous systems must pay a great deal of attention to the dynamic state of the circuit.  ...  Acknowledgments This paper has been greatly improved by a number of patient readers, including Gaetano Borriello, John Brzozowski, Al Davis, David Dill, Carl Ebeling, Jo Ebergen, Henrik Hulgaard, Carl  ... 
doi:10.1109/5.362752 fatcat:2wtrcnhd3beeve2vzcuij6vydq

Synthesis of Asynchronous Hardware from Petri Nets [chapter]

Josep Carmona, Jordi Cortadella, Victor Khomenko, Alex Yakovlev
2004 Lecture Notes in Computer Science  
This paper focuses on some of recent developments and new opportunities for Petri nets in designing asynchronous circuits such as synthesis of asynchronous control circuits from large Petri nets generated  ...  They include direct mapping of Petri nets to circuits, structural methods with linear programming, and synthesis from unfolding prefixes using SAT solvers.  ...  More formal definition of Signal Transition Graphs To be able to introduce the methods of synthesis of asynchronous circuits in subsequent sections, we will need a more formal definition of an STG .  ... 
doi:10.1007/978-3-540-27755-2_9 fatcat:z4dgiwj54be5bacubhptl3uggq

The tides of EDA

A. Sangiovanni-Vincentelli
2003 IEEE Design & Test of Computers  
The great success of circuit simulation in IC designs has been a dominant driver in the birth of EDA as an industry.  ...  Exploiting the quasi-unidirectional characteristic of a MOS transistor to speed up circuit simulation first appeared in the work of Gummel and colleagues of Bell Labs in 1975.  ...  These researchers used peephole rule-based optimization to generate efficient gate-level representations of a design.  ... 
doi:10.1109/mdt.2003.1246165 fatcat:mbu6motr3nbcxoavgt3zrdlzb4

Semi-Explicit Parallel Programming in a Purely Functional Style: GpH [chapter]

2008 Process Algebra for Parallel and Distributed Processing  
This series aims to capture new developments and applications in the field of computational science through the publication of a broad range of textbooks, reference works, and handbooks.  ...  The scope of the series includes, but is not limited to, titles in the areas of scientific computing, parallel and distributed computing, high performance computing, grid computing, cluster computing,  ...  Their diligent and conscientious efforts not only helped us to make the final selection of chapters but also provided numerous valuable suggestions to the authors, resulting in a high-quality collection  ... 
doi:10.1201/9781420064872-9 fatcat:znq5b5h47zeblbzv4bclttpfoi

A burst-mode oriented back-end for the Balsa synthesis system

T. Chelcea, A. Bardsley, D. Edwards, S.M. Nowick
Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition  
This paper introduces several new component clustering techniques for the optimization of asynchronous systems.  ...  Experimental results on several substantial design examples, including an 32-bit microprocessor core, indicate significant performance improvements for the optimized circuits.  ...  The section ends with a discussion of the formal verification of these optimizations, and also with a summary of the optimization algorithms.  ... 
doi:10.1109/date.2002.998294 dblp:conf/date/ChelceaNBE02 fatcat:edmgso5w7rbfdkotlyiojhxz64

Logic Synthesis [chapter]

2017 Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology  
Nowick, Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems, Design Automation Conference, New Orleans, Louisiana, USA, 2002, pp. 405-410. 41. A. J.  ...  C.A.J. van Eijk, Formal methods for the veri�cation of digital circuits, PhD thesis, Eindhoven University of Technology, Eindhoven, the Netherlands, 1997. 59. E.I. Goldberg, M.K.  ... 
doi:10.1201/9781315215112-13 fatcat:me52zpnxyfcczh3choo2p4zulm

Single-rail handshake circuits

A. Peeters, K. van Berkel
Proceedings Second Working Conference on Asynchronous Design Methodologies  
In a post-optimization step these are eliminated. Peephole optimization Especially at the gate-level netlist, peephole optimization is of utmost importance.  ...  Another approach that might help is to exploit the richness of the genetic library through peephole optimization. Low power is considered to be the key strength of asynchronous circuits.  ...  In order to understand the reason bebind these handicaps we should have more · insight into the design of asynchronous circuits, especially into the approach that is pursued at the Nat.Lab.  ... 
doi:10.1109/wcadm.1995.514642 dblp:conf/async/PeetersB95 fatcat:hh5n3hsh7jfa3izk7x4jot54qa

Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits

M.A. Pena, J. Cortadella
Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems  
We propose a new approach based on the composition of Petri nets and the automatic synthesis through Signal Transition Graphs that allows to take advantage of logic synthesis methods to optimize the circuit  ...  This paper presents a new methodology to automatically synthesize asynchronous circuits from descriptions based on process algebra.  ...  Introduction Process algebras have been successfully used for the specification and formal verification of digital asynchronous circuits.  ... 
doi:10.1109/async.1996.494453 dblp:conf/async/PenaC96 fatcat:fkm5rxxbcvaxflsnmhqsykofuq

Foundations of scientific research (Foundations of Research Activities) [article]

N. M. Glazunov
2012 arXiv   pre-print
During years 2008 to 2011 author gives several courses on Foundations of Scientific Research at Computer Science Faculty of the National Aviation University in Kiev.  ...  Some sections of the text contain enough material to lectures, but in some cases these are sketchs without references to Foundations of Research Activities.  ...  Some examples of scopes include:  Peephole optimizations: Usually performed late in the compilation process after machine code has been generated.  ... 
arXiv:1212.1651v1 fatcat:e3oe5neztff5vjlj4trchbi3qa

Synthesis Of Concurrent System Interface Modules With Automatic Protocol Conversion Generation

B. Lin, S. Vercauteren
IEEE/ACM International Conference on Computer-Aided Design  
In this paper, we describe a new high-level compiler called Integral that can be used for the automated design of such system interface modules.  ...  This permits a non-expert designer to specify high-level communication between modules without a detailed understanding of the actual communication protocol characteristics employed in each individual  ...  Related Work Automated logic synthesis tools have been developed for the synthesis of asynchronous control circuits [3, 6, 10, 11, 12, 18] .  ... 
doi:10.1109/iccad.1994.629751 dblp:conf/iccad/LinV94 fatcat:kopkpw2x4fettadsw3ktlwvbc4
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