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Formal Verification of Hardware Synthesis [chapter]

Thomas Braibant, Adam Chlipala
2013 Lecture Notes in Computer Science  
We report on the implementation of a certified compiler for a high-level hardware description language (HDL) called Fe-Si (FEatherweight SynthesIs).  ...  The target language of the compiler corresponds to a synthesisable subset of Verilog or VHDL.  ...  Part of this research was done while the first author was visiting MIT from University of Grenoble. This material is based on research sponsored by DARPA under agreement number FA8750-12-2-0110.  ... 
doi:10.1007/978-3-642-39799-8_14 fatcat:pcphv4i37vfmpmiax5zi2xzkl4

Formal synthesis in circuit design — A classification and survey [chapter]

Ramayya Kumar, Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid
1996 Lecture Notes in Computer Science  
We also briefly introduce our own approach towards the formal synthesis of hardware. Finally, we compare these approaches from different points of view.  ...  This article gives a survey on different methods of formal synthesis.  ...  Acknowledgements The authors are grateful to the anonymous referees whose constructive comments have improved the quality of the paper.  ... 
doi:10.1007/bfb0031817 fatcat:bz6cob6jd5bo3izawypciavotq

Issues in Tool Qualification for Safety-Critical Hardware: What Formal Approaches Can and Cannot Do [chapter]

Brian Butka, Janusz Zalewski, Andrew J. Kornecki
2009 Lecture Notes in Computer Science  
This paper examines what is unique to hardware design, areas where formal methods can be applied to advantage in hardware design and how errors can exist in the hardware even if formal methods are used  ...  Technology has improved to the point that system designers have the ability to trade-off implementing complex functions in either hardware or software.  ...  Findings contained herein are not necessarily those of the FAA.  ... 
doi:10.1007/978-3-642-04468-7_17 fatcat:kecmx2fqbzdcroisstidgpcpl4

ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions [chapter]

Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik
2019 Lecture Notes in Computer Science  
The ILA formal model targeting the hardware-software interface enables a clean separation of concerns between software and hardware through a unified model for heterogeneous processors and accelerators  ...  Topdown it provides a specification for functional verification of hardware, and bottom-up it provides an abstraction for software/hardware coverification.  ...  The simulator can be a software/hardware prototype and is used as an oracle during ILA synthesis. The synthesis algorithm fills in the missing parts in the set of instructions.  ... 
doi:10.1007/978-3-030-17462-0_21 fatcat:eh2w44eg55forkmdlz2jud7abu

High-Level Synthesis: Status, Trends, and Future Directions

Andres Takach
2016 IEEE design & test  
The key to enable more efficient productivity for both design and verification is to raise the level of abstraction.  ...  The use of application-specific hardware accelerators are one of the most promising ways to keep power consumption in check while delivering increasing levels of functionality and performance.  ...  Verification of the hardware relies on the use of a combination of simulation, formal, FPGA prototyping, and emulation techniques.  ... 
doi:10.1109/mdat.2016.2544850 fatcat:3b2oil4vijbwjgrji7agavddqa

Automatic Post-Synthesis Verification Support for a High Level Synthesis Step by using the HOL Theorem Proving System [chapter]

Matthias Mutz
1997 IFIP Advances in Information and Communication Technology  
The higher order logic theorem proving system HOL is used to define formal hardware models, to define an implementation relation between these models, and to develop the verification procedure.  ...  The paper discusses the development of automatic post-synthesis verification support for a high level synthesis step.  ...  We also exploit the knowledge about formal aspects of synthesis steps but we do not have to interfere with the synthesis tools. This is a well known advantage of post-synthesis verification methods.  ... 
doi:10.1007/978-0-387-35190-2_19 fatcat:veqbp6f5ojbclmbygzctrpmqbm

Preface

Sabine Glesner, Jens Knoop, Rolf Drechsler
2007 Electronical Notes in Theoretical Computer Science  
Moreover, special emphasis is put on embedded systems, in particular on hardware verification, formal synthesis methods, correctness aspects in HW/SW co-design and formal verification of hardware/software  ...  hardware synthesis and verification.  ...  The paper by Bloem, Galler, Jobstmann, Piterman, Pnueli and Weiglhofer proposes a formal specification language for hardware synthesis and shows that it allows for the efficient synthesis of compact circuits  ... 
doi:10.1016/j.entcs.2007.09.003 fatcat:ap4er7l3ynhrroxhqtoyzvnali

Machine Learning for Automated Synthesis of Complex Software

Susmit Jha
2012 Journal of Information Technology & Software Engineering  
However, little effort has been directed towards the automated synthesis of correct-by-construction software by leveraging complementary strengths of formal verification and modern machine learning techniques  ...  between machine learning and formal verification.  ... 
doi:10.4172/2165-7866.1000e113 fatcat:rk3mlaizmngtniljo2f2nsnltq

Embedded computing - Formal methods in embedded design

S.D. Johnson
2003 Computer  
A BEACHHEAD IN PRACTICE: HARDWARE VERIFICATION In the early 1980s, a branch of formal methods research coalesced around digital hardware.  ...  To enable automated reasoning, the hardware simulation languages superimpose synchronous dialects for verification and synthesis.  ... 
doi:10.1109/mc.2003.1244539 fatcat:wctoe3stwrfttc6webv6usdd54

Formal methods for engineering special-purpose parallel systems introduction to minitrack

A.E. Abdallah, W. Luk
2003 36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of the  
synthesis, simulation, and formal verification.  ...  The paper Formal Behavioural Synthesis of Handel-C Parallel Hardware Implementations from Functional Specifications by A. Abdallah and J.  ...  synthesis, simulation, and formal verification.  ... 
doi:10.1109/hicss.2003.1174807 fatcat:5ckhdatqzzh5tnysh7eeq6ieku

Assertion checkers - enablers of quality design

Marc Boule, Zeljko Zilic
2008 2008 1st Microsystems and Nanoelectronics Research Conference  
field of logic design and verification.  ...  This paper outlines the MBAC tool for the generation of assertion checkers in hardware.  ...  Fig. 2 . 2 Assertion Checkers in Hardware Verification, Silicon Debugging and On-Line Monitoring. Fig. 3 . 3 Using Checkers in Formal (Static) and Dynamic Verification.  ... 
doi:10.1109/mnrc.2008.4683387 fatcat:ir6crrkn4bfu3fjagngsruwhiu

RAM Special Issue on Formal Methods for Robotics and Automation

2010 IEEE robotics & automation magazine  
While formal methods have been successfully applied to areas such as hardware design, the unique nature of robotics requires new theory and algorithms for verification and synthesis of correct systems.  ...  model checking and deductive verification techniques in robotics • Correct by design planner/controller synthesis • Lessons that can be learned from hardware/software verification and synthesis • Applications  ... 
doi:10.1109/mra.2010.938856 fatcat:mv2qqzkrkrempiywwmytamhlha

High-Level Verification

Sudipta Kundu, Sorin Lerner, Rajesh Gupta
2009 IPSJ Transactions on System LSI Design Methodology  
The high-level verification approaches address verification of properties as well as equivalence checking with refined implementations.  ...  In this paper, we present a survey of high-level verification techniques that are used for both verification and validation of high-level designs, that is, designs modeled using high-level programming  ...  Earlier surveys on formal verification in hardware design 38),49), 61) give more comprehensive details about the theoretical and application aspects of it for RTL designs.  ... 
doi:10.2197/ipsjtsldm.2.131 fatcat:xb27xitplbgppig6z5galpr6ue

Firmware quality assurance

Helmut K. Berg, Prakash Rao, Bruce D. Shriver
1982 Proceedings of the June 7-10, 1982, national computer conference on - AFIPS '82  
The emphasis of the paper is on formal correctness proofs, firmware testing, and the automatic synthesis of microcode and associated hardware structures.  ...  The paper reviews problems, solutions, and trends in the area of firmware quality assurance.  ...  We restrict our attention to areas of formal firmware correctness proofs, firmware testing, and the automatic synthesis of microcode and associated hardware structures.  ... 
doi:10.1145/1500774.1500776 dblp:conf/afips/BergRS82 fatcat:wg5ytjwyyjdhxa2qqbpxiq3zga

IEEE and RAS Awards

2010 IEEE robotics & automation magazine  
While formal methods have been successfully applied to areas such as hardware design, the unique nature of robotics requires new theory and algorithms for verification and synthesis of correct systems.  ...  model checking and deductive verification techniques in robotics • Correct by design planner/controller synthesis • Lessons that can be learned from hardware/software verification and synthesis • Applications  ... 
doi:10.1109/mra.2010.938857 fatcat:5idtetgyljcvzl4jdxoostnuqq
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