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Formal Verification of Explicitly Parallel Microprocessors [chapter]

Byron Cook, John Launchbury, John Matthews, Dick Kieburtz
1999 Lecture Notes in Computer Science  
Techniques from formal verification have been used to automate the test generation for a dual-issue DLX microprocessor [16] which can be viewed as a simple explicitly parallel machine.  ...  It is therefore natural that the verification of explicitly parallel microarchitectures will be similar to the verification of superscalar out-of-order machines -with a twist.  ...  f act is a (p, s,ps, l)-frozen version of 7£f act , and therefore the termination of 7?.f act implies that of 7?.fact • The following 7?| act is the 5-erasure of 7lJ act for 5 = {ps-p-1}.  ... 
doi:10.1007/3-540-48153-2_4 fatcat:pd5w6ggq6fdpxfeqwiprqxintu

Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description

Luka Charvat, Ale Smrcka, Toma Vojnar
2012 2012 13th International Workshop on Microprocessor Test and Verification (MTV)  
The paper proposes an automated approach with a formal basis designed for checking correspondence between an RTL implementation of a microprocessor and a description of its instruction set architecture  ...  Although the approach does not provide full formal verification, experiments with the approach confirm that due to a different way it explores the state space of the design under test, it can find bugs  ...  Therefore, a use of formal verification is desirable even if it is applied in a bounded way. Unfortunately, formal verification is not a common part of the current microprocessor design tool chains.  ... 
doi:10.1109/mtv.2012.19 dblp:conf/mtv/CharvatSV12 fatcat:tx5hiqdq3renjnp2o3diolxpdy

HADES: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems

Lukáš Charvát, Aleš Smrčka, Tomáš Vojnar
2016 Electronic Proceedings in Theoretical Computer Science  
HADES is a fully automated verification tool for pipeline-based microprocessors that aims at flaws caused by improperly handled data hazards.  ...  It has been successfully tested on several microprocessors for embedded applications.  ...  Formal verification of such microprocessors-despite they are much simpler than common processors for mainstream computing-is a very challenging task.  ... 
doi:10.4204/eptcs.233.9 fatcat:o6s5q5h3c5hujly63vxebyhlfq

Scalable hybrid verification of complex microprocessors

Maher Mneimneh, Fadi Aloul, Chris Weaver, Saugata Chatterjee, Karem Sakallah, Todd Austin
2001 Proceedings of the 38th conference on Design automation - DAC '01  
This verification approach enables the practical deployment of formal methods without impacting overall performance.  ...  We introduce a new verification methodology for modern microprocessors that uses a simple checker processor to validate the execution of a companion high-performance processor.  ...  PREVIOUS WORK Formal microprocessor verification methods represent an alternative to traditional verification by simulation.  ... 
doi:10.1145/378239.378265 dblp:conf/dac/MneimnehAWCSA01 fatcat:qp2cnhdprvdadnlmkvrwzkzkzq

Challenges in processor modeling and validation [Guest Editors' introduction]

P. Bose, T.M. Conte, T.M. Austin
1999 IEEE Micro  
Validation issues Current microprocessor design teams use a combination of simulation-based and formal verification techniques to validate (functionally) the RTL and pre-RTL models.  ...  On the other hand, Hunt and Sawada highlight the promise of formal specification and verification by describing their work in verifying an actual pipelined, superscalar microprocessor.  ...  His work includes productoriented research for future-generation microprocessors, development of university relations, and design and implementation of performance analysis tools.  ... 
doi:10.1109/mm.1999.768495 fatcat:jfxhc7zbsrhcrfdzr575xsnp2a

Improvement of Algebraic Models of Abstract Pipelines for Formal Verification

2018 Academic Journal of Computing & Information Science  
microprocessors formal verification.  ...  A systematic approach to model microprocessors and their correctness is useful and necessary for practical projects of formal verifications.  ...  It forms a basis of uniform theoretical frameworks for modeling microprocessors, and simplifies the actual processes of formal verification.  ... 
doi:10.25236/ajcis.010006 fatcat:bz3fgyekk5e7tfqwvvt27yr6xi

Verification-Aware Microprocessor Design

Anita Lungu, Daniel J. Sorin
2007 Parallel Architecture and Compilation Techniques (PACT), Proceedings of the International Conference on  
Using Cadence SMV, a composite formal verification tool that combines model checking and theorem proving, we explore several aspects of processor design, including caches, TLBs, pipeline depth, ALUs, and  ...  The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable.  ...  We believe that this paper is the first work to explicitly address the issue of verification-aware design for microprocessors.  ... 
doi:10.1109/pact.2007.4336202 fatcat:2234v5g6ejhahblumiv5ch4ot4

UniTESK: Component Model Based Testing

Alexander K. Petrenko, Victor V. Kuliamin, Andrey Maksimov
2013 International Conference on Information and Communication Technologies in Education, Research, and Industrial Applications  
UniTESK is a testing technology based on formal models or formal specifications of requirements to the behavior of software and hardware components.  ...  The most significant applications of UniTESK in industrial projects are described, the experience is summarized, and the prospective directions to the Component Model Based Testing development are estimated  ...  It allows targeting on specific kinds of optimizations. In the case of microprocessor design verification, the MicroTESK tool [19, 20, 21] was developed.  ... 
dblp:conf/icteri/PetrenkoKM13 fatcat:a56672qpenektppaardtrdn5ye

Verifying x86 Instruction Implementations [article]

Shilpi Goel, Anna Slobodova, Rob Sumners, Sol Swords
2019 arXiv   pre-print
Despite significant progress in formal verification, the goal of complete verification of an industrial design has not been achieved.  ...  Verification of modern microprocessors is a complex task that requires a substantial allocation of resources.  ...  Indeed, the best approach for applying formal verification resources in microprocessor verification is divide-and-conquer.  ... 
arXiv:1912.10285v1 fatcat:aeocsrtb5zd6vfsqklcoi3stxy

Reflections on the Future of Concurrency Theory in General and Process Calculi in Particular

Hubert Garavel
2008 Electronical Notes in Theoretical Computer Science  
This suggests a new generation of formal specification languages that would combine the concurrent features of process calculi with the standard concepts present in algorithmic languages.  ...  As a tentative classification, we can mention: Models to represent the behaviour of concurrent systems: Petri nets, Labelled Transition Systems, Kripke structures, event structures, bigraphs, etc., Formalisms  ...  As regards microprocessors, the limits of Moore's law are about to be reached.  ... 
doi:10.1016/j.entcs.2008.04.009 fatcat:cj2gvg3xsvg7jbcztlbktujm6a

Low voltage swing logic circuits for a Pentium® 4 processor integer core

Daniel J. Deleganes, Micah Barany, George Geannopoulos, Kurt Kreitzer, Anant P. Singh, Sapumal Wijeratne
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
Low Voltage Swing logic circuits implemented in 90nm technology[2] meet the frequency demands of a third generation integer-core design.  ...  INTRODUCTION Microprocessor performance can be defined as the product of latency and parallelism.  ...  RTL codes equivalent equations that are formally verified against the schematic versions. As illustration, the rotator/shifter described later exceeds 42,000 paths for verification.  ... 
doi:10.1145/996566.996751 dblp:conf/dac/DeleganesBGKSW04 fatcat:r7xu4mhmy5bktjqrsrtdudu6m4

A Rewriting Semantics for ABEL with Applications to Hardware/Software Co-Design and Analysis

Michael Katelman, José Meseguer
2007 Electronical Notes in Theoretical Computer Science  
The formal properties of the hardware, the embedded software, and the interactions between both can all be analyzed this way. We present two case studies illustrating our method and tool.  ...  We present a rewriting logic semantics in Maude of the ABEL hardware description language.  ...  In addition, we thank Sean Keller for reviewing a draft of the paper, and Andrew Colombi for a version of the graphics program. This research has been supported in part by ONR grant N00014-02-1-0715.  ... 
doi:10.1016/j.entcs.2007.06.007 fatcat:eopiwss46ncwxhmjjvnh4dktwy

Algebraic Models of Correctness for Microprocessors

A. C. J. Fox, N. A. Harman
2000 Formal Aspects of Computing  
These maps are defined by equations which evolve a system from an initial state by the iterative application of a next-state function. A formal model of time is used in the form of a clock algebra.  ...  In this paper we present a method of describing microprocessors at different levels of temporal and data abstraction.  ...  The work on microprocessor representation will be unified with the closely-related work of K Stephenson on languages and compilers Stephenson [1996] : in particular, work on the Java Virtual Machine .  ... 
doi:10.1007/pl00003936 fatcat:nnhzjlrvk5hodaeo53bo3ukkaa

Formal Verification of Designs with Complex Control by Symbolic Simulation [chapter]

Gerd Ritter, Hans Eveking, Holger Hinrichsen
1999 Lecture Notes in Computer Science  
The verification tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decision-diagram based techniques, with increasing accuracy in order to optimize overall verification  ...  A new approach for the automatic equivalence checking of behavioral or structural descriptions of designs with complex control is presented.  ...  Prominent examples are the verification of the FM9001 microprocessor [4] using Nqthm, of the Motorola CAP processor [5] using ACL2 and the verification of the AAMP5 processor using PVS [23] .  ... 
doi:10.1007/3-540-48153-2_18 fatcat:xikff34jmzcjpc3gwqqvo5azfy

Industrial hardware and software verification with ACL2

Warren A. Hunt, Matt Kaufmann, J Strother Moore, Anna Slobodova
2017 Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences  
We also wish to thank Sol Swords for helpful feedback on a draft of this paper, and to thank the many sponsors of the ACL2 group at the University of Texas at Austin, including NSF and DARPA.  ...  ., for its continuing support of the ACL2 project.  ...  Symbolic simulation [31] of the formal RTL model (in SVEX form) is at the core of the Centaur formal verification method.  ... 
doi:10.1098/rsta.2015.0399 pmid:28871049 fatcat:7bdhr5s6srdrjm6aonktjsm7qq
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