7 Hits in 2.0 sec

Bounded Model Checking for Region Automata [chapter]

Fang Yu, Bow-Yaw Wang, Yao-Wen Huang
2004 Lecture Notes in Computer Science  
In: Proceedings of the Joint Conference on Formal Modelling and Analysis of Timed Systems and Formal Techniques in Real-Time and Fault Tolerant System (FORMATS-FTRTFT 2004), LNCS 3253, pages 246-262, Grenoble  ...  In: Proceedings of the 23rd IFIP International Conference on Formal Techniques for Networked and Distributed Systems (FORTE 2003), LNCS 2767, Berlin, Sept.-Oct. 2003.  ... 
doi:10.1007/978-3-540-30206-3_18 fatcat:g5sawav6rvbtfntyihfbjtp3re

Contents EATCS bulletin number 59, June 1996

1996 Theoretical Computer Science  
Foundations of Computer Science (MFCS '96), Cracow, Poland, 2-6 Fourth International School and Symposium on Formal Techniques in Real Time and Fault Tolerant Systems (FTRTFT '96), Uppsala, Sweden  ...  Working Group on Formal Methods for Industrial Critical Systems, Oxford, United Kingdom, 19 March 1996 (report by D.  ... 
doi:10.1016/s0304-3975(96)90089-4 fatcat:qjudqhsagfguhggbsgcv7feweq

Contents EATCS bulletin number 57, October 1995

1995 Theoretical Computer Science  
Fourth International School and Symposium on Formal Techniques in Real Time and Fault Tolerant Systems (FTRTFT '96), Uppsala, Sweden, 9-13 September 1996 . .  ...  Vajnovszki: Constant Time Generation of Binary Unordered Trees 14. Surveys and Tutorials Hierarchy of Discrete-Time Dynamical Systems, a Survey (by F. Geurts) . . 15.  ... 
doi:10.1016/0304-3975(95)90168-x fatcat:7hmlddprzbanhodm7e3gmstyba

Verification methods for the divergent runs of clock systems [chapter]

Thomas A. Henzinger, Peter W. Kopke
1994 Lecture Notes in Computer Science  
We classify all real-time systems into an in nite hierarchy, according to how w ell they admit the translation of eventuality properties into equivalent safety properties.  ...  We present a methodology for proving temporal properties of the divergent runs of reactive systems with real-valued clocks. A run diverges if time advances beyond any bound.  ...  Appendix A.1 A region-system eventuality p r o o f Consider the program Wait5 from the introduction, which loops waiting until ve units of time pass. We prove that Wait5 j = div 3(x = 0 ) .  ... 
doi:10.1007/3-540-58468-4_173 fatcat:2jsfx36oivf6rpbieton6iab5m

Almost-Sure Model Checking of Infinite Paths in One-Clock Timed Automata

Christel Baier, Nathalie Bertrand, Patricia Bouyer, Thomas Brihaye, Marcus GröBer
2008 Logic in Computer Science  
We prove that these two semantics match in the framework of single-clock timed automata (and only in that framework), and prove that the corresponding relaxed model-checking problems are PSPACE-Complete  ...  In this paper, we define two relaxed semantics (one based on probabilities and the other one based on the topological notion of largeness) for LTL over infinite runs of timed automata which rule out unlikely  ...  We assume that there exists a fair infinite path π such that dim(π) = and π |= ϕ, and show that the set ϕ fair is not large. This fair infinite path π ends up in a BSCC of G b (A).  ... 
doi:10.1109/lics.2008.25 dblp:conf/lics/BaierBBBG08 fatcat:s4nuvm24brbhralnrvii2hhypy

Verification of the cryptlib Kernel [chapter]

Cryptographic Security Architecture  
Methods", Constance Heitmeyer, Proceedings of the 5 th International Symposium on Formal Techniques in Real-Time and Real-Time Fault-Tolerant Systems (FTRTFT'98), Springer-Verlag Lecture Notes in Computer  ...  and development, specifically for use with event-driven real-time systems.  ... 
doi:10.1007/0-387-21551-4_5 fatcat:hc53bwbkfzevflnpqtai2fu2ke

A simple proof checker for real-time systems

Catherine Leung
A simple proof checker with built-in decision procedures for linear programming and predicate calculus offers a pragmatic approach to verifying real-time systems in return for a slight loss of formal rigor  ...  This thesis presents a practical approach to verifying real-time properties of V L S I designs.  ...  In particular, this thesis examines the application of formal methods to the verification of real-time systems.  ... 
doi:10.14288/1.0051212 fatcat:oa4wcckxirfddksvyqdcwrkjca