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Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume

Songwei Pei, Huawei Li, Xiaowei Li
2012 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Index Terms-Fault coverage, flip-flop selection, launch on capture (LOC), partial enhanced scan, test data volume reduction.  ...  We propose a flip-flop selection method to reduce the overall volume of transition delay test data, by replacing a small number of selected regular scan cells with enhanced scan cells.  ...  [11] presented a partial enhanced scan technique with a flip-flop selection strategy for increasing the transition delay coverage.  ... 
doi:10.1109/tvlsi.2011.2170227 fatcat:rdv3pswjrjhyxn7dawoalba4cq

A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs

Seongmoon Wang, S.T. Chakradhar
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Instead of topology-based approaches used in prior publications, the proposed technique uses a special ATPG to identify pairs of adjacent scan flip-flops between which test points are inserted to improve  ...  In this paper, an automatic test pattern generator (ATPG)-based scan-path test point insertion technique, which can achieve high delay fault coverage for scan designs, is proposed.  ...  In order to reduce area overhead, partial enhanced scan technique where only selected scan flip-flops are replaced by enhanced scan flip-flops is proposed by [2] .  ... 
doi:10.1109/tcad.2005.855929 fatcat:sf74vzqfqjfo3kfe3pfojeqvoi

A critical-path-aware partial gating approach for test power reduction

Mohammed Elshoukry, Mohammad Tehranipoor, C. P. Ravikumar
2007 ACM Transactions on Design Automation of Electronic Systems  
We propose an alternate solution where a partial set of scan cells is gated. A subset of scan cells is selected to give maximum reduction in test power within a given area constraint.  ...  Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results.  ...  If BC is used along with SeqTD, then the only way that delay fault testing can be done is by using enhanced scan [Bushnell and Agrawal 2000] .  ... 
doi:10.1145/1230800.1230809 fatcat:m4fzi3xtdbfq3fqxkn6qtpw6ee

Eliminating the Timing Penalty of Scan

Ozgur Sinanoglu, Vishwani D. Agrawal
2013 Journal of electronic testing  
In this work, we propose a pair of scan cell transformation techniques that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer  ...  Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan in a cost-effective way and thus enhancing the functional speed of integrated circuits  ...  The pattern to be loaded into the untransformed scan cells and shadow flip-flops is the two patterns merged together: the pattern for stuck-atv fault on the original flip-flop input and the pattern for  ... 
doi:10.1007/s10836-013-5352-5 fatcat:xlgaetbu55dwjda6cwimbxuwbe

Power-oriented partial-scan design approach

J.–Y. Jou, M.–C. Nien
1998 IEE Proceedings - Circuits Devices and Systems  
A full-scan method had been used widely in the past, to improve the testability of sequential circuits. Owing to the lower overheads incurred, the partial-scan design has gradually become popular.  ...  , the saving of overheads for each specific cost function is significant.  ...  As discussed so far, we can use the switching activity of flip-flops as a new measurement for the selection of scan flip-flops in partial-scan design.  ... 
doi:10.1049/ip-cds:19981920 fatcat:kjw7xgtkvvdmdh5qgyvzybhrdq

Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan

Kim Le, Dong Baik, Kewal Saluja
2007 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)  
In this paper we propose an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delayfault tests.  ...  In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design.  ...  Reddy for providing the test sets used in this paper.  ... 
doi:10.1109/vlsid.2007.156 dblp:conf/vlsid/LeBS07 fatcat:74malekbbjeu5ngkwfaa6sbul4

Efficient test-point selection for scan-based BIST

Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, S. Bhawmik
1998 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In addition, a symbolic procedure is proposed to compute testability measures more efficiently for circuits with feedbacks so that the test point selection algorithm can be applied to partial-scan circuits  ...  We propose a test point selection algorithm for scanbased built-in self-test (BIST).  ...  For full-scan BIST, all flip-flops are replaced; for partial-scan BIST, flip-flops which will convert the circuit into an NAC after scanning them are replaced with scan flip-flops.  ... 
doi:10.1109/92.736140 fatcat:bh354hwvxnh2jhlivpax62tzjm

Test-point insertion: scan paths through functional logic

Chih-Chang Lin, M. Marek-Sadowska, Kwang-Ting Cheng, M.T.-C. Lee
1998 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design.  ...  We show an algorithm that uses the new test-point insertion technique to reduce the area overhead for the full-scan design. We also discuss its application to the timing-driven partial-scan design.  ...  In [20] , a timing-driven partial-scan flip-flop selection algorithm was proposed.  ... 
doi:10.1109/43.720319 fatcat:cx72aafyg5bbdn75i5n3ks6x6m

Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra

Prasenjit Biswas, D. M. H. Walker
2017 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)  
Scan-based delay test achieves high fault coverage due to its improved controllability and observability. This is particularly important for our K Longest Paths  ...  In our experiments, the flip-flops have been converted to non-scan arbitrarily. The actual impact on path recovery will be more visible with realistic selection of non-scan flip-flops.  ...  In a scan based test, a scan chain isformed by serially connecting the sequential elements of the circuit. The flip-flops that are part of the chain are called scan flip-flops (SFFs).  ... 
doi:10.1109/vlsid.2017.63 dblp:conf/vlsid/BiswasW17 fatcat:ubblzc2kvrdhxbbzqmzbc464ye

Multi-cycle Test with Partial Observation on Scan-Based BIST Structure

Yasuo Sato, Hisato Yamaguchi, Makoto Matsuzono, Seiji Kajihara
2011 2011 Asian Test Symposium  
We evaluate a multi-cycle test method that observes the values of partial flip-flops on a chip during capture-mode.  ...  This paper proposes a novel technique that improves fault coverage or reduces the number of test vectors that is needed for achieving the given fault coverage on scan-based BIST structure.  ...  Yoshinobu Higami, Ehime University, Japan, for his invaluable discussion in fault simulation of sequential circuits.  ... 
doi:10.1109/ats.2011.34 dblp:conf/ats/SatoYMK11 fatcat:63jakg3mqrgctay7jbr6m7naje

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

Hanan T. Al-AWADHI, Tomoki AONO, Senling WANG, Yoshinobu HIGAMI, Hiroshi TAKAHASHI, Hiroyuki IWATA, Yoichi MAEDA, Jun MATSUSHIMA
2020 IEICE transactions on information and systems  
The FF-CPI technique modifies the captured values of scan Flip-Flops (FFs) during capture operation by directly reversing the value of partial FFs or loading random vectors.  ...  The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of FF-CPI technique in scan-in pattern reduction for POST.  ...  Regarding the FF selection methods referred to TrPI, LIMA and HEM for FF-CPI proposed in Sect. 4, the effects of TrPI and LIMA for scan-in pattern reduction might be depend on the circuits used for testing  ... 
doi:10.1587/transinf.2019edp7235 fatcat:hnq5wtv3tvd2nclhomt6zb6ibe

Power-safe test application using an effective gating approach considering current limits

Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty
2011 29th VLSI Test Symposium  
The toggling rate reduction tendency is demonstrated to be useful in estimating how much extra logic is needed to achieve a desired shift power reduction rate for a design.  ...  Freezing scan cell outputs can block transitions to the combinational components thus reduce shift power.  ...  Now let us consider the impact of inserted logic on capture power. D pin of each flip-flop is fed by combinational logic, and its value will impact the transition on next arriving cycle.  ... 
doi:10.1109/vts.2011.5783777 dblp:conf/vts/ZhaoTC11 fatcat:nckq2ugttnfejczkzvjxt73m6i

Functionally testable path delay faults on a microprocessor

Wei-Cheng Lai, A. Krstic, Kwang-Ting Cheng
2000 IEEE Design & Test of Computers  
One way to resolve this problem is using built-in self-test  ...  Ensuring that designs meet performance specifications requires application of delay tests.  ...  A structural test for a path is a test applied through the (enhanced or standard) full-scan chain.  ... 
doi:10.1109/54.895002 fatcat:jfvko2p7hzal3lazsaaacyeofa

A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time

Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic
2012 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Furthermore, a dummy scan flip-flop insertion procedure is proposed aiming at decreasing transition generation time.  ...  This paper analyzes time to generate a transition in functional Trojans. Transition is modeled by geometric distribution and the number of clock cycles required to generate a transition is estimated.  ...  When Test Enable (TE pin) is active, the output of scan flip-flop is supplied by Scan Input (SI pin). The inserted dummy scan flip-flop has no impact on the functionality of the circuit.  ... 
doi:10.1109/tvlsi.2010.2093547 fatcat:5mzonh5hrfgnnbifk5euvmtaae

An Introduction to Logic Circuit Testing

Parag K. Lala
2008 Synthesis Lectures on Digital Circuits and Systems  
This may limit the fault coverage obtained by using the technique. The selection flip-flops to be included in the partial scan is done by heuristic methods.  ...  Such flip-flops are identified as controllable flip-flops. Figure 3 .24 shows a sequential circuit modified for enhanced controllability.  ...  TeST PATTerN GeNerATIoN For bIST Author biography  ... 
doi:10.2200/s00149ed1v01y200808dcs017 fatcat:vm4fduadpfcodcjwr4vtzdac6i
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