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Flexible Working Memory through Selective Gating and Attentional Tagging

Wouter Kruijne, Sander M. Bohte, Pieter R. Roelfsema, Christian N. L. Olivers
2020 Neural Computation  
As such, WorkMATe provides a new solution for the neural implementation of flexible memory control.  ...  Furthermore, the control strategies that the model acquires for these tasks subsequently generalize to new task contexts with novel stimuli, thus bringing symbolic production rule qualities to a neural  ...  to a new context with novel stimuli.  ... 
doi:10.1162/neco_a_01339 pmid:33080159 fatcat:k36y5cux4zajtixpigrxfi5uwy

Flexible working memory through selective gating and attentional tagging [article]

Wouter Kruijne, Sander M. Bohte, Pieter R. Roelfsema, Christian N. L. Olivers
2019 bioRxiv   pre-print
Furthermore, the control strategies that the model acquires for these tasks subsequently generalize to new task contexts with novel stimuli.  ...  Here, we present WorkMATe, a neural network architecture that implements flexible cognitive control and learns to apply these control mechanisms using a biologically plausible reinforcement learning method  ...  B Memory unit within a block, with a 'closed' gate: the memory content is maintained via self-recurrent connections.  ... 
doi:10.1101/846675 fatcat:wrv2cqqyrvgn5newjlk5iawz2y

Context-modular memory networks support high-capacity, flexible, and robust associative memories [article]

William F Podlaski, Everton J Agnes, Tim P Vogels
2020 bioRxiv   pre-print
Furthermore, memories can be biased to have different relative strengths, or even gated on or off, according to contextual cues, providing a candidate model for cognitive control of memory and efficient  ...  An external context-encoding network can dynamically switch the memory network to a desired state, which we liken to experimentally observed contextual signals in prefrontal cortex and hippocampus.  ...  This work was supported by a Sir Henry Dale Fellowship by the Wellcome Trust and the Royal Society (WT100000; WFP, EJA and TPV),  ... 
doi:10.1101/2020.01.08.898528 fatcat:q776gdynrfdpzadwoetzy6lia4

The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework [article]

Nastaran Hajinazar, Pratyush Patel, Minesh Patel, Konstantinos Kanellopoulos, Saugata Ghose, Rachata Ausavarungnirun, Geraldo Francisco de Oliveira Jr., Jonathan Appavoo, Vivek Seshadri, Onur Mutlu
2020 arXiv   pre-print
of translation requests and associated memory accesses; and (2) two heterogeneous main memory architectures, where VBI increases the effectiveness of managing fast memory regions.  ...  To address these challenges, we propose a new virtual memory framework, the Virtual Block Interface (VBI).  ...  heterogeneous main memory architectures.  ... 
arXiv:2005.09748v1 fatcat:fuzajm73gvgjjj7eerrhiyvkwu

Adaptive and flexible dictionary code compression for embedded applications

Mats Brorsson, Mikael Collin
2006 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06  
Dictionary code compression is a technique where long instructions in the memory are replaced with shorter code words used as index in a table to look up the original instructions.  ...  Previous work with dictionary code compression has shown decent performance and energy savings results which we verify with our own measurement that are more thorough than previously published.  ...  system L1 I-cache L1 D-cache TLB (D&I) Main memory 16kB, 2-way, 32 byte blocks, 1 cycle latency 16kB, 2-way, 32 byte blocks, 1 cycle latency 128 entry, 4-way, 30 cycle miss penalty 64 cycle latency  ... 
doi:10.1145/1176760.1176776 dblp:conf/cases/BrorssonC06 fatcat:vslvyejsu5gvrcrtkncz4jbeha

A Flexible Heterogeneous Multi-Core Architecture

Miquel Pericas, Adrian Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jimenez, Mateo Valero
2007 Parallel Architecture and Compilation Techniques (PACT), Proceedings of the International Conference on  
This allows to overcome the memory wall for applications with high memory-level parallelism (MLP).  ...  This paper proposes the Flexible Heterogeneous Mul-tiCore processor (FMC), the first dynamic heterogeneous multi-core architecture capable of reconfiguring itself to fit application requirements without  ...  Daniel A. Jiménez is supported by NSF Grant CCF-0545898.  ... 
doi:10.1109/pact.2007.4336196 fatcat:uuhhokn2bzcypkrk4ptz5izno4

NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps [article]

Alessandro Aimar, Hesham Mostafa, Enrico Calabrese, Antonio Rios-Navarro, Ricardo Tapiador-Morales, Iulia-Alexandra Lungu, Moritz B. Milde, Federico Corradi, Alejandro Linares-Barranco, Shih-Chii Liu, Tobi Delbruck
2018 arXiv   pre-print
We propose a flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios.  ...  We implemented the proposed architecture on a Xilinx Zynq FPGA platform and present results showing how our implementation reduces external memory transfers and compute time in five different CNNs ranging  ...  Thus, it achieves a speedup directly proportional to a CNN's sparsity since it does not waste cycles on zero input pixels, while preserving a high level of CNN architecture flexibility.  ... 
arXiv:1706.01406v2 fatcat:epm6g7fgdnesbmni4i4gjsg75a

Transactional memory

Håkan Grahn
2010 Journal of Parallel and Distributed Computing  
Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip.  ...  In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task.  ...  Each memory block has a number of tokens associated with it.  ... 
doi:10.1016/j.jpdc.2010.06.006 fatcat:s3qswzin6jhoneph7taqsnxoxe

Energy-Efficient In-Memory Database Computing

Wolfgang Lehner
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
We argue that-even after 30 years of active database research-the time is right to rethink some of the core architectural principles and come up with novel approaches to meet the requirements of the next  ...  Within the last few years, the database community sparked a large number of extremely innovative research projects to push the envelope in the context of modern database system architectures.  ...  [9] is giving a wealth of other database-related problems for GPU usage. • Large-scale main-memory management: Commodity servers equipped with 1 TByte main memory are currently available for a very  ... 
doi:10.7873/date.2013.105 dblp:conf/date/Lehner13 fatcat:bo6yc73o65gbfmtaeanlh726wq

CodeX: Bit-Flexible Encoding for Streaming-based FPGA Acceleration of DNNs [article]

Mohammad Samragh, Mojan Javaheripi, Farinaz Koushanfar
2019 arXiv   pre-print
CodeX full-stack framework comprises of a compiler which takes a high-level Python description of an arbitrary neural network architecture.  ...  CodeX incorporates nonlinear encoding to the computation flow of neural networks to save memory.  ...  Memory Compression In quantization, a finite set of best representatives (a.k.a. bins) are selected and each real-valued number is approximated with the closest bin.  ... 
arXiv:1901.05582v1 fatcat:l4lsuogaknhwlpcbyncbich42q

NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps

Alessandro Aimar, Hesham Mostafa, Enrico Calabrese, Antonio Rios-Navarro, Ricardo Tapiador-Morales, Iulia-Alexandra Lungu, Moritz B. Milde, Federico Corradi, Alejandro Linares-Barranco, Shih-Chii Liu, Tobi Delbruck
2018 IEEE Transactions on Neural Networks and Learning Systems  
We propose a flexible and efficient CNN accelerator architecture which can support the implementation of SOA CNNs in low-power and low-latency application scenarios.  ...  The flexible architecture allows full utilization of available computing resources across a wide range of convolutional network kernel sizes; and numbers of input and output feature maps.  ...  NullHop allows sparse computation with high utilization comparable to pipelines operating on dense representations.  ... 
doi:10.1109/tnnls.2018.2852335 pmid:30047912 fatcat:pmkgmoeowrhdphfsy667a75nm4

Memory Analysis of Low Power MPEG-4 Decoder Architecture

Andreas Dahlin, Johan Ersfolk, Haitham Habli, Johan Lilius
2009 2009 International Conference on Embedded Software and Systems  
The reason has been attributed to overheads in software, and in the context of multi-media codecs a new approach has been proposed.  ...  In this paper we analyse the approach for its memory requirements, and propose some optimisations that will substantially decrease the memory bandwidth of the approach. 2009 International Conferences on  ...  The architecture, illustrated in Figure 5 features a general purpose processor connected to the main memory through a system bus.  ... 
doi:10.1109/icess.2009.85 dblp:conf/icess/DahlinEHL09 fatcat:tgjuequvdbgzbafxmkguy5h7ke

Hardware Supported Flexible Monitoring: Early Results [chapter]

Atonia Zhai, Guojin He, Mats P. E. Heimdahl
2009 Lecture Notes in Computer Science  
The framework must also allow low-level monitoring and be highly flexible so we can accommodate a broad range of crucial monitoring activities.  ...  To achieve our goals, we have pursued an approach leveraging the rapid emergence of multicore processor architectures to achieve a non-intrusive, predictable, finegrained, and highly flexible general purpose  ...  ] to achieve a non-intrusive, predictable, fine-grained, and highly flexible general purpose monitoring framework through monitoring-aware compilers coupled with novel architectural enhancements to the  ... 
doi:10.1007/978-3-642-04694-0_12 fatcat:tmt4xzudwfez7fkxjnf3ymjtwi

Near-Memory Address Translation

Javier Picorel, Djordje Jevdjic, Babak Falsafi
2017 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)  
Traditionally, the memory hierarchy comprises two levels, main memory and secondary memory. • Main memory: The main memory, often called random access memory (RAM), is directly connected to the central  ...  Therefore, a conventional two-level TLB hierarchy, a first level with 64 entries and a second level with 1024 is a sound approach.  ...  QFlex is composed of three main components: QEMU, Flexus, and NS-3.  ... 
doi:10.1109/pact.2017.56 dblp:conf/IEEEpact/PicorelJF17 fatcat:zgsfj7v4pjazdcfb5hcyemndea

Eclipse: heterogeneous multiprocessor architecture for flexible media processing

M.J. Rutten, J.T.J. van Eijndhoven, E.D. Pol Egbert, G.T. Jaspers, P. van der Wolf, O.P. Gangwal, A. Timmer
2002 Proceedings 16th International Parallel and Distributed Processing Symposium  
Intended as a scalable and flexible subsystem of forthcoming media-processing systems-on-a-chip, Eclipse combines application configuration flexibility with the efficiency of function-specific hardware  ...  This paper presents the Eclipse architecture template as well as a first instantiation with coprocessors that support simultaneous MPEG-2 encoding and decoding. † Evert-Jan Pol is currently with Philips  ...  The Eclipse architecture has been explored in a first instantiation for simultaneous MPEG-2 encoding and decoding of multiple streams at various resolutions.  ... 
doi:10.1109/ipdps.2002.1016517 dblp:conf/ipps/RuttenEPJWGT02 fatcat:h66rcwhjv5e4pm5jyggrjqaxva
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