Filters








5,557 Hits in 5.8 sec

Flexible Hardware Acceleration for Instruction-Grain Program Monitoring

Shimin Chen, Michael Kozuch, Theodoros Strigkos, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Olatunji Ruwase, Michael Ryan, Evangelos Vlachos
2008 2008 International Symposium on Computer Architecture  
In this paper, we propose a flexible hardware solution for accelerating a wide range of instruction-grain monitoring tools.  ...  Instruction-grain program monitoring tools, which check and analyze executing programs at the granularity of individual instructions, are invaluable for quickly detecting bugs and security attacks and  ...  We thank Anastassia Ailamaki, Limor Fix, Greg Ganger, Michelle Goodstein, Bin Lin, and Radu Teodorescu for their contributions and inputs to the LBA project.  ... 
doi:10.1109/isca.2008.20 dblp:conf/isca/ChenKSFGMRRRV08 fatcat:sf6a6h723zdpbkp2ymdlxmb67u

Flexible Hardware Acceleration for Instruction-Grain Program Monitoring

Shimin Chen, Evangelos Vlachos, Michael Kozuch, Theodoros Strigkos, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Olatunji Ruwase, Michael Ryan
2008 SIGARCH Computer Architecture News  
In this paper, we propose a flexible hardware solution for accelerating a wide range of instruction-grain monitoring tools.  ...  Instruction-grain program monitoring tools, which check and analyze executing programs at the granularity of individual instructions, are invaluable for quickly detecting bugs and security attacks and  ...  We thank Anastassia Ailamaki, Limor Fix, Greg Ganger, Michelle Goodstein, Bin Lin, and Radu Teodorescu for their contributions and inputs to the LBA project.  ... 
doi:10.1145/1394608.1382153 fatcat:auj2fmes3vcihejabwgdfsxlei

Flexible Hardware Acceleration for Instruction-Grain Lifeguards

Shimin Chen, Michael Kozuch, Phillip B. Gibbons, Michael Ryan, Theodoros Strigkos, Todd C. Mowry, Olatunji Ruwase, Evangelos Vlachos, Babak Falsafi, Vijaya Ramachandran
2009 IEEE Micro  
We thank Anastassia Ailamaki, Limor Fix, Greg Ganger, Michelle Goodstein, Bin Lin, and Radu Teodorescu for their contributions to the LBA project.  ...  of parallel programming), it also provides the much-needed hardware resources to include architectural support for instruction-grain monitoring.  ...  INSTRUCTION-GRAIN LIFEGUARDS MONITOR EXECUTING PROGRAMS AT THE GRANULARITY OF INDIVIDUAL INSTRUCTIONS TO QUICKLY DETECT BUGS AND SECURITY ATTACKS, BUT THEIR FINE-GRAIN NATURE INCURS HIGH MONITORING OVERHEADS  ... 
doi:10.1109/mm.2009.6 fatcat:apesvolhqzbbtn2rs7ff3g533q

FADE: A programmable filtering accelerator for instruction-grain monitoring

Sotiria Fytraki, Evangelos Vlachos, Onur Kocberber, Babak Falsafi, Boris Grot
2014 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)  
As existing software approaches incur prohibitive runtime overhead, researchers have focused on hardware support for instruction-grain monitoring.  ...  Instruction-grain monitoring is a powerful approach that enables a wide spectrum of bug-finding tools.  ...  Software dynamic instruction-grain monitoring tools afford high flexibility, but they slow down program execution by up to two orders of magnitude [16] .  ... 
doi:10.1109/hpca.2014.6835922 dblp:conf/hpca/FytrakiVKFG14 fatcat:nc4v4tuuefftvo3ji4miiuymeu

High-performance parallel accelerator for flexible and efficient run-time monitoring

Daniel Y. Deng, G. Edward Suh
2012 IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)  
This paper proposes Harmoni, a high performance hardware accelerator architecture that can support a broad range of run-time monitoring and bookkeeping functions.  ...  Harmoni takes moderate silicon area, has very high throughput, and incurs low overheads on monitored programs.  ...  Our on-chip accelerator architecture, named Harmoni (Hardware Accelerator for Runtime MONItoring), provides an efficient realization of the general tagging model.  ... 
doi:10.1109/dsn.2012.6263925 dblp:conf/dsn/DengS12 fatcat:qdoiyu6i2fdafocud2sw3vp54u

Operating Systems Should Manage Accelerators

Sankaralingam Panneerselvam, Michael M. Swift
2012 USENIX Conference on Hot Topics in Parallelism  
The inexorable demand for computing power has lead to increasing interest in accelerator-based designs.  ...  An accelerator is specialized hardware unit that can perform a set of tasks with much higher performance or power efficiency than a general-purpose CPU.  ...  Acknowledgements We thank the anonymous reviewers for their feedback and also like to thank Mohit Saxena and Vijay Chidambaram for their comments on the earlier drafts of the paper.  ... 
dblp:conf/hotpar/PanneerselvamS12 fatcat:zxw2735zazbbvmn2ggggybcvse

Dynamic Information Flow Tracking: Taxonomy, Challenges, and Opportunities

Kejun Chen, Xiaolong Guo, Qingxu Deng, Yier Jin
2021 Micromachines  
Based on the analysis, we classify the existing solutions into three categories, i.e., software, hardware, software and hardware co-design.  ...  Dynamic information flow tracking (DIFT) has been proven an effective technique to track data usage; prevent control data attacks and non-control data attacks at runtime; and analyze program performance  ...  However, it lacks enough flexibility for security policy reconfiguration for different program contexts.  ... 
doi:10.3390/mi12080898 fatcat:zfkiddrjvbfjli7ht6x5jgyp7q

Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric

Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh
2010 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture  
At the same time, FlexCore is far more efficient than software implementations because its fine-grained reconfigurable architecture closely matches bitlevel operations of typical monitoring schemes and  ...  Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into a modern microprocessor, the FlexCore architecture allows parallel monitoring and bookkeeping  ...  To address such inefficiencies, Chen et al. proposed a set of hardware acceleration techniques for run-time monitoring on multi-cores [11] .  ... 
doi:10.1109/micro.2010.17 dblp:conf/micro/DengLMSS10 fatcat:htxhhfdrmvfm3lwbqtlditg22i

Trusted computing - A new challenge for embedded systems

Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Alain Pegatoquet
2006 2006 13th IEEE International Conference on Electronics, Circuits and Systems  
In this paper we propose a thorough overview of processor-based solutions to protect programs and data exchanges within embedded systems.  ...  The most significant part of the work for the monitor is to protect the accesses to data. Several hardware mechanisms have been added to the architecture to support this feature.  ...  Hardware security engines can be subdivided in three categories: coprocessors, accelerators and dedicated processors.  ... 
doi:10.1109/icecs.2006.379904 dblp:conf/icecsys/VaslinGDP06 fatcat:ys6si4vxy5fklfts6tf24zqdoq

Log-based architectures

Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Todd C. Mowry
2011 ACM SIGOPS Operating Systems Review  
To help detect and fix software bugs, we have been exploring techniques for accelerating dynamic program monitoring tools, which we call "lifeguards".  ...  To accomplish this, we propose hardware mechanisms to create a dynamic log of instruction-level events in the monitored application and stream this information to one or more software lifeguards running  ...  The authors thank Babak Falsafi, Michelle Goodstein, Olatunji Ruwase and Evangelos Vlachos for their collaboration on the LBA project.  ... 
doi:10.1145/1945023.1945034 fatcat:rilpizgqlnetdophuh6ttfgks4

Hardware Supported Flexible Monitoring: Early Results [chapter]

Atonia Zhai, Guojin He, Mats P. E. Heimdahl
2009 Lecture Notes in Computer Science  
To address this fundamental software engineering challenges, we propose a compiler and hardware supported framework for monitoring and observation of software-intensive systems.  ...  We use separate cores for the execution of the application to be monitored and the monitors.  ...  Recently, there have been proposals for hardware support for a variety of monitoring activities; in particular to support fine-grained monitoring.  ... 
doi:10.1007/978-3-642-04694-0_12 fatcat:tmt4xzudwfez7fkxjnf3ymjtwi

PHMon: A Programmable Hardware Monitor and Its Security Use Cases

Leila Delshadtehrani, Sadullah Canakci, Boyou Zhou, Schuyler Eldridge, Ajay Joshi, Manuel Egele
2020 USENIX Security Symposium  
In this paper, we propose a minimallyinvasive and efficient implementation of a Programmable Hardware Monitor (PHMon) with expressive monitoring rules and flexible fine-grained actions.  ...  In contrast to this trend, a flexible hardware monitor can efficiently enforce and enhance a variety of security policies as security threats evolve.  ...  We program one MU (MU0) to monitor call instructions and another MU (MU1) to monitor ret instructions.  ... 
dblp:conf/uss/DelshadtehraniC20 fatcat:msjv6wkmnjbynh4nzewmazpzuu

Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management

Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu
2004 Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04  
The MultiFlex tools map these models onto the StepNP multi-processor SoC platform, while making use of harware accelerators for message passing and task scheduling.  ...  A number of multi-processor programming models designed for SoC scale application have been presented.  ...  They also experimented with a partial hardware acceleration for scheduling and lock management, and observe efficiencies approaching 63%.  ... 
doi:10.1145/1016720.1016735 dblp:conf/codes/PaulinPLBN04 fatcat:3z4uri2ef5bctk2p3yhe7ilcye

Software transparent dynamic binary translation for coarse-grain reconfigurable architectures

Matthew A. Watkins, Tony Nowatzki, Anthony Carno
2016 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)  
custom hardware and the flexibility of software.  ...  In this work we propose DORA, a Dynamic Optimizer for Reconfigurable Architectures, which achieves substantial (2X) power and performance improvements while having low hardware and insertion overhead and  ...  ACKNOWLEDGMENTS We thank Karu Sankaralingam for his feedback as this work developed and for comments on draft versions of the paper.  ... 
doi:10.1109/hpca.2016.7446060 dblp:conf/hpca/WatkinsNC16 fatcat:ssmt2kzalba2xoozatcp6imlxq

Decoupled lifeguards

Olatunji Ruwase, Shimin Chen, Phillip B. Gibbons, Todd C. Mowry
2010 SIGPLAN notices  
Flexible Hardware Acceleration for Instruction-grain Program Monitoring. In Proceedings of the 35th Annual International Symposium on Technical Reports O. Ruwase, P.B. Gibbons, M.A. Kozuch, T.C.  ...  Research Experience Fall 2006-2013 Improving Studied techniques for accelerating runtime correctness checking by optimizing how hot program paths are monitored. Presented results at PLDI 2010.  ... 
doi:10.1145/1809028.1806600 fatcat:sv2frxhrdzfdxpenteni222rsu
« Previous Showing results 1 — 15 out of 5,557 results