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Flexible Decoupled Transactional Memory Support

Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott
2008 2008 International Symposium on Computer Architecture  
Specifically, our FlexTM (FLEXible Transactional Memory) system introduces conflict summary tables (CSTs) to concisely capture conflicts between transactions.  ...  We present a system, FlexTM (FLEXible Transactional Memory), that employs three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary  ...  Unbounded Space Support To provide the illusion of unbounded space to transactions, the underlying system needs to support transactions in the presence of (1) L1 cache overflows and (2) physical memory  ... 
doi:10.1109/isca.2008.17 dblp:conf/isca/ShriramanDS08 fatcat:kwyihhdwpbentfbnd4anoqzaei

Flexible Decoupled Transactional Memory Support

Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott
2008 SIGARCH Computer Architecture News  
Specifically, our FlexTM (FLEXible Transactional Memory) system introduces conflict summary tables (CSTs) to concisely capture conflicts between transactions.  ...  We present a system, FlexTM (FLEXible Transactional Memory), that employs three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary  ...  Unbounded Space Support To provide the illusion of unbounded space to transactions, the underlying system needs to support transactions in the presence of (1) L1 cache overflows and (2) physical memory  ... 
doi:10.1145/1394608.1382134 fatcat:hnt46ouzcba3hhlrjeywq6jbrq

Parallel SystemC simulation for ESL design using flexible time decoupling

Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid
2015 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
Recently published parallel SystemC simulators use time-decoupling to achieve high simulation performance on modern SMP machines.  ...  This work presents an approach how to overcome this limitation and to enable time-decoupled simulation for mainstream SystemC simulators, achieving a speedup of up to 3.4× on a quad-core host. • Enable  ...  Acknowledgments This work has been supported by the CHIST-ERA project GEMSCLAIM.  ... 
doi:10.1109/samos.2015.7363702 dblp:conf/samos/WeinstockLA15 fatcat:gnkboasj2bcfddp7hchx2nxlle

DudeTM

Mengxing Liu, Mingxing Zhang, Kang Chen, Xuehai Qian, Yongwei Wu, Weimin Zheng, Jinglei Ren
2017 Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '17  
DUDETM uses shadow DRAM to decouple the execution of a durable transaction into three fully asynchronous steps.  ...  However, existing durable transaction systems employ either undo logging, which requires a fence for every memory write, or redo logging, which requires intercepting all memory reads within transactions  ...  This work is supported by Natural Science Founda  ... 
doi:10.1145/3037697.3037714 dblp:conf/asplos/LiuZCQWZR17 fatcat:5vqrfqdt4vferptfsl5fykwhwe

ARIES/NT Modification for Advanced Transactions Support [chapter]

Henrietta Dombrowska
1996 Workshops in Computing  
A modification of ARIES/NT algorithm for nested transactions rollback and recovery is proposed.  ...  This modification allows to perform the forward recovery for advanced transaction models, such as ConTracts and some subclasses of Sagas.  ...  Figure 1 : 1 Advanced Transaction Classes Figure 2 : 2 Locking and Latching other flexible transaction models, namely, decoupled and deffered transactions, split transactions, and some other.  ... 
doi:10.1007/978-1-4471-1486-4_4 dblp:conf/adbis/Dombrowska95 fatcat:p3ckjwpy7bhotmc2h2bs3veizy

Transaction local aliasing in storage class memory

Ellis Giles, Kshitij Doshi, Peter Varman
2015 2015 IEEE International Conference on Networking, Architecture and Storage (NAS)  
The decoupling of concurrency control (or transaction isolation) from failure atomicity allows persistence to be added flexibly to code that is already multi-threading safe.  ...  An early presentation of SoftWrAP technique [4] was introduced in [3] , and a similar approach for supporting transactional writes to persistent memory is described in REWIND [2] , which offers a more  ... 
doi:10.1109/nas.2015.7255242 dblp:conf/nas/GilesDV15 fatcat:wgejqzvroveyvcq3yfj2wsuozq

Heterogeneous multi-core platform for consumer multimedia applications

P. Kollig, C. Osborne, T. Henriksson
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
usage of a heterogeneous multi-core SoC platform is presented and it is shown how specific challenges such as inter-processor communication and real-time performance guarantees in physically centralized memory  ...  Functional subsystems such as transport stream (TS) de-multiplexing or video decode are decoupled by paths through the main memory.  ...  Softening of real time constraints through memory decoupling reduces overall system integration effort and reduces risk of dynamic system behavior issues.  ... 
doi:10.1109/date.2009.5090857 dblp:conf/date/KolligOH09 fatcat:owaqbujdtvh6tlgts563yfe2ru

Manticore: A User-Friendly Symbolic Execution Framework for Binaries and Smart Contracts [article]

Mark Mossberg, Felipe Manzano, Eric Hennenfent, Alex Groce, Gustavo Grieco, Josselin Feist, Trent Brunson, Artem Dinaburg
2019 arXiv   pre-print
Manticore's flexible architecture allows it to support both traditional and exotic execution environments, and its API allows users to customize their analysis.  ...  ARCHITECTURE Manticore's design is highly flexible and supports both traditional computing environments (x86/64, ARM) and exotic ones, such as the Ethereum platform.  ...  Despite these differences, adding Ethereum support did not require substantial architectural changes to Manticore, since the Core Engine is completely decoupled from all execution platform details. 1)  ... 
arXiv:1907.03890v3 fatcat:jac7d4akzvhq3nl7d4qyylrqqy

High performance RISC microprocessors

J. Choquette, M. Gupta, D. McCarthy, J. Veenstra
1999 IEEE Micro  
With the intellectual property in place, the architecture will proliferate and show that low cost and flexibility do not have to come at the cost of compromising performance.  ...  We had to assess well-defined attributes such as performance, cost, power, time-to-market, tools support, and portability within this philosophy to help define the architecture.  ...  This allows pipelining of multiple memory requests and decouples memory transactions from the processor execution.  ... 
doi:10.1109/40.782567 fatcat:vehrfcamdndh5fxelu2cyjm2le

Object-oriented framework for high-performance electronic medical imaging

Douglas C. Schmidt, Timothy H. Harrison, Irfan Pyarali, V. Ralph Algazi, Sadayasu Ono, Andrew G. Tescher
1996 Very High Resolution and Quality Imaging  
The Blob Streaming framework and its applications are decoupled from various types of storage (such as file, memory, and databases).  ...  To support a wide spectrum of radiological workflow efficiently, the EMIS must be flexible.  ... 
doi:10.1117/12.233040 fatcat:gg3dld3ojbd45fml52lsiqtczq

A Software-defined SoC Memory Bus Bridge Architecture for Disaggregated Computing [article]

Dimitris Syrivelis, Andrea Reale, Kostas Katrinis, Christian Pinto
2018 arXiv   pre-print
A key property of the proposed bridge architecture is that it is software-defined and thus can be configured at runtime, via a software control plane, to prepare and steer memory access transactions to  ...  Moreover, we evaluate a bridge prototype we have build for ARM AXI4 memory bus interconnect and we discuss application-level observed performance.  ...  Current SoC memory bus architectures [2] [18] provide totally decoupled communication between many masters and slaves.  ... 
arXiv:1801.03712v1 fatcat:pcen6ymz5fe3dcct4eyx6lrwsy

Decoupled hardware support for distributed shared memory

Steven K. Reinhardt, Robert W. Pfile, David A. Wood
1996 SIGARCH Computer Architecture News  
This paper investigates hardware support for fine-grain distributed shared memory (DSM) in networks of workstations.  ...  To reduce design time and implementation cost relative to dedicated DSM systems, we decouple the functional hardware components of DSM support, allowing greater use of off-the-shelf devices.  ...  To exploit the flexibility of software protocol processing, both decoupled designs run user-level protocol handlers and support the Tempest interface [35] .  ... 
doi:10.1145/232974.232979 fatcat:xlvt3pco3vakrhow3fr5taaefy

High-Performance and Lightweight Transaction Support in Flash-Based SSDs

Youyou Lu, Jiwu Shu, Jia Guo, Shuai Li, Onur Mutlu
2015 IEEE transactions on computers  
The no-overwrite property of flash memory naturally supports transactions, a commonly used mechanism in systems to provide consistency.  ...  Experiments show that LightTx achieves nearly the lowest overhead in garbage collection, memory consumption and mapping persistence compared to existing embedded transaction designs.  ...  In this section, we mainly focus on transaction support with flash memory.  ... 
doi:10.1109/tc.2015.2389828 fatcat:lffclmyosrb3botf6vmphk3jo4

Decoupled hardware support for distributed shared memory

Steven K. Reinhardt, Robert W. Pfile, David A. Wood
1996 Proceedings of the 23rd annual international symposium on Computer architecture - ISCA '96  
This paper investigates hardware support for fine-grain distributed shared memory (DSM) in networks of workstations.  ...  To reduce design time and implementation cost relative to dedicated DSM systems, we decouple the functional hardware components of DSM support, allowing greater use of off-the-shelf devices.  ...  To exploit the flexibility of software protocol processing, both decoupled designs run user-level protocol handlers and support the Tempest interface [35] .  ... 
doi:10.1145/232973.232979 dblp:conf/isca/ReinhardtPW96 fatcat:3brtvx2ihjcczkrrqbw7qj6wra

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood
2005 SIGARCH Computer Architecture News  
We leverage an existing full-system functional simulation infrastructure (Simics [14]) as the basis around which to build a set of timing simulator modules for modeling the timing of the memory system  ...  We thank Virtutech AB, the Wisconsin Condor group, and the Wisconsin Computer Systems Lab for their help and support.  ...  This work is supported in part by the National Science Foundation (CCR-0324878, EIA/CNS-0205286, and CCR-0105721) and donations from Compaq, IBM, Intel Corporation and Sun Microsystems.  ... 
doi:10.1145/1105734.1105747 fatcat:5vqwipjnrjfddmllpknvycdzz4
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