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Associative Memories and Processors: The Exact Match Paradigm
1999
Journal of King Saud University: Computer and Information Sciences
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It comprises of two level s of distinction, the associative memory organization and the processing capability which heavily depend s on the application domain. ...
Associative or content addressable memories (CAM) are crucial in the implementation of high performance computing architectures for applications that require intensive data management or are cognitive ...
The inherent SIMD processing and array oriented data structure in associative computing architectures make them attractive for such real time applications. ...
doi:10.1016/s1319-1578(99)80003-2
fatcat:b2vlhax5gzgpbd7hnxejhtrjqm
50 & 25 Years Ago
2019
Computer
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Flag-Oriented Parallel Associative Architectures and Applications (p. 41) "A flag-oriented architecture contains one processing unit capable of executing complex functions in parallel." ...
An Optical Associative Parallel Processor for High-Speed Database Processing (p.65) "This architecture exploits optics to perform word-parallel and bit-parallel relative magnitude searches. ...
doi:10.1109/mc.2019.2933688
fatcat:upqlhq3vtjczlf2seijgiier5q
Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks
2015
2015 IEEE International Symposium on Circuits and Systems (ISCAS)
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Furthermore, we present the corresponding hardware architecture and implementation of the new approach in comparison with a conventional architecture in literature, and show that the proposed architecture ...
In this paper, we propose a new pattern retrieval algorithm that results in a dramatically lower error rate compared to that of the conventional approach when used in oriented edge detection process. ...
ACKNOWLEDGMENT This work has received a French government support granted to the CominLabs excellence laboratory and managed by the National Research Agency in the "Investing for the Future" program under ...
doi:10.1109/iscas.2015.7169193
dblp:conf/iscas/DaniloJGCCG15
fatcat:pz3roke5knfdxj5nqjgvlz3mj4
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems
2006
2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
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This mechanism is proposed to improve the performance of the application specific instruction-set processors (ASIP) we develop customized to an object-oriented application. ...
In addition, by adding a prefetch flag to cache blocks, we eliminate a large number of prefetch related tag comparisons. ...
The architecture is specifically designed to suit object-oriented (OO) applications. ...
doi:10.1109/icsamos.2006.300802
dblp:conf/samos/HessabiMGJ06
fatcat:e475clxwrvbwnibftafseha3de
Associative Processor Architecture---a Survey
1977
ACM Computing Surveys
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Based on their architecture, associative processors are classified into four categories, namely fully parallel, bit-serial, word-serial and block-oriented. ...
The fully parallel associative processors are divided into two classes, word-orgamzed and distributed logic associative processors. ...
The four categories are fully parallel, bit-serial, wordserial, and block-oriented associative processors. ...
doi:10.1145/356683.356685
fatcat:zp5acsurkvhhlmdnv6keycjzyu
Flagged Parallel Manipulators
2007
IEEE Transactions on robotics
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The conditions for a parallel manipulator to be flagged can be simply expressed in terms of linear dependencies between the coordinates of its leg attachments, both on the base and on the platform. ...
The main interest of flagged parallel manipulators is that their singularity loci admit a well-behaved decomposition with a unique topology irrespective of the metrics of each particular design. ...
Therefore, the identification of the singularity loci of parallel robots is a very important design and application issue. ...
doi:10.1109/tro.2007.903819
fatcat:exygzhzi7zetfd5axcnx4odrtq
A unified design methodology for offline and online testing
1998
IEEE Design & Test of Computers
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Independent of computer system configuration, it facilitates easy changes of test algorithms and implementations. ...
associative memory and processor architectures introduced by Tavangarian, 6 maps word-oriented data into flag-oriented data. ...
The approach proposed here extends some of the online test techniques based on flag-oriented parallel associative architectures and merges them with a system test design approach successfully implemented ...
doi:10.1109/54.679210
fatcat:frz4gi46zzfg3au33mdzh6kasu
Architectural Support on Object-Oriented Programming in a JAVA Processor
2006
IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
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Java is widely applied in mobile devices and network applications due to its object-oriented features and corresponding advantages such as security, robustness, platform independence. ...
In this paper, a Java processor architecture named jHISC is proposed, which implements the features of object-oriented programming by hardware directly and executes the object-oriented instructions much ...
The Caltech Object Machine (COM) [6] , which was oriented to the late binding object-oriented programming language, provided hardware method lookup and maintained addressing information in an associative ...
doi:10.1109/asap.2006.16
dblp:conf/asap/YiyuYF06
fatcat:bsdhveaaanhrfgx4flo5r62cou
Scalable shared-memory multiprocessor architectures
1990
Computer
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Acknowledgment We would like to thank all the authors of the special reports that follow for their assistance and for their review of this introduction. ...
This memory organization al-
lows a simpler programming model, mak-
ing it easier to develop new parallel appli-
cations or to move existing applications
from a uniprocessor to a parallel system. ...
They also excel in multiprogramming throughput-oriented environments. ...
doi:10.1109/2.55502
fatcat:bi7hzoeqarbsvjrj2ldtdig5ry
Stratifications of the Euclidean motion group with applications to robotics
2008
Geometriae Dedicata
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We prove that classically known cell decompositions of the flag manifold restricted to the open subset parameterizing the affine real flags are still stratifications, and we introduce a refinement of the ...
In this paper we derive stratifications of the Euclidean motion group, which provide a complete description of the singular locus in the configuration space of a family of parallel manipulators, and we ...
Figure 5 : 5 The three possible architectures for the 3-3 parallel manipulators: (a) octahedral, (b) flagged and (c) partially-flagged. ...
doi:10.1007/s10711-008-9341-2
fatcat:lesln72vd5baxemt3nnpu2n2pi
Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems
2011
IEICE transactions on information and systems
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These SIMD matrix architectures are verified to be a better alternative for processing repeated-arithmetic and logical-operations in multimedia applications with low power consumption. ...
The massive-parallel memory-embedded SIMD matrix architecture (MTX and MX-2) is therefore a promising solution for integrated realization of real-time cryptographic algorithms with low power dissipation ...
Okuno and K. Arimoto of Renesas Technology Co. for their support. ...
doi:10.1587/transinf.e94.d.1742
fatcat:ccjkqgp64bhj3agq5f6qpuk45y
A Hardware/Software Co-design and Co-verification on a Novel Embedded Object-Oriented Processor
[chapter]
2005
Lecture Notes in Computer Science
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is a novel object-oriented processor which provides a natural way to map the concept of OOP into architectural level through the hardware object data structure. ...
OOP), where objects are the key elements to build up application and the communications between different objects are through method invocation. ...
These fields are, Address Field, Access Modifier, Type Field, Static Flag, Read Only Flag, and Resolved Flag. ...
doi:10.1007/11596356_39
fatcat:g4dilz75bvc4pg762dh5ffbdji
A Code-level Parallelization Methodology to Enhance Interactivity of Smartphone Entertainment Applications
스마트폰 엔터테인먼트 애플리케이션의 상호작용성 개선을 위한 코드 수준 병렬화 방법론
2015
Journal of Digital Convergence
스마트폰 엔터테인먼트 애플리케이션의 상호작용성 개선을 위한 코드 수준 병렬화 방법론
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This paper proposes a methodology to boost responsiveness of interactive applications by taking advantage of the parallel architecture of mobile devices which, for instance, have dual-core, quad-core or ...
The mobile device such as the smartphone, however, does not guarantee it due to the limit of the application processor's computing power, memory size and available electric power of the battery. ...
Thus it could enhance various real-world applications' performance by fully utilizing the device's parallel architecture. ...
doi:10.14400/jdc.2015.13.12.381
fatcat:5dwocisqsze7vobnbyys2jefei
A Java processor with hardware-support object-oriented instructions
2006
Microprocessors and microsystems
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In jHISC, 94% of Bytecodes and 83% of the object-oriented related Bytecodes are implemented by hardware directly. ...
Java is widely applied from the small embedded devices to enterprise systems nowadays due to its object-oriented features and corresponding advantages of security, robustness, and platform independence ...
The authors thank Mok Pak Lun, Lo Kai Man, and Yu Wing Shing for their invaluable consultation. ...
doi:10.1016/j.micpro.2005.12.007
fatcat:g5yz5st44nccbfco6kjlsiie2y
A high performance Streams-based architecture for communication subsystems
[chapter]
1995
IFIP Advances in Information and Communication Technology
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We show how communication channels simplify the main data paths and how they improve both Streams flow control and parallelization. ...
In the fourth section we present an architecture to solve these problems and discuss performance measurements. ...
Special thanks to Michel Habert from Bull and Christian Huitema from INRIA for the interest they showed in that project and for their advice. ...
doi:10.1007/978-0-387-34885-8_5
fatcat:tgymbtjh2bagtjagmt5qlrojru
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