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Fine-Grained Caching of Verification Results [chapter]

K. Rustan M. Leino, Valentin Wüstholz
2015 Lecture Notes in Computer Science  
To increase the responsiveness of the program verifier during such interactions, we designed a system for fine-grained caching of verification results.  ...  The caching system uses the program's call graph and controlflow graph to focus the verification effort on just the parts of the program that were affected by the user's most recent modifications.  ...  We are grateful to the users of the Dafny IDE-notably, Nada Amin, Maria Christakis, Arjun Narayan, and Bryan Parno-for providing feedback on its caching system.  ... 
doi:10.1007/978-3-319-21690-4_22 fatcat:kppunm4xdbf3bmhpx2gdnbrye4

An Evaluation of Coarse-Grained Locking for Multicore Microkernels [article]

Kevin Elphinstone, Amirreza Zarrabi, Adrian Danis, Yanyan Shen, Gernot Heiser
2016 arXiv   pre-print
locks, enable formal verification, and still achieve scalability comparable to fine-grained locking.  ...  Coarse-grained locking provides lower overhead under low contention, fine-grained locking provides higher scalability under contention, though at the expense of implementation complexity and re- duced  ...  Owing to the implementation of TSX, the RTM lock logically protects a dynamic set of individual L1 and L2 cache lines, and as such is a fairly extreme case of fine-grained locking, which should result  ... 
arXiv:1609.08372v2 fatcat:erghtyzjrfgwddddefwz45w7ri

On the parallel execution time of tiled loops

K. Hogstedt, L. Carter, J. Ferrante
2003 IEEE Transactions on Parallel and Distributed Systems  
This paper presents results of experimental research on possibilities of estimating the execution time of coarse-grained parallel program loops based on a regression model.  ...  The intended use of the model in question is iterative compilation. Streszczenie.  ...  There are two types of granularity (hence, parallelism): coarse-grained granularity (coarsegrained parallelism) and fine-grained granularity (finegrained parallelism).  ... 
doi:10.1109/tpds.2003.1189587 fatcat:bedm55cnqje2xinr5p7act4n4e

Process-shared and persistent code caches

Derek Bruening, Vladimir Kiriansky
2008 Proceedings of the fourth ACM SIGPLAN/SIGOPS international conference on Virtual execution environments - VEE '08  
Inter-process sharing of code caches significantly improves the ability to efficiently apply code caching tools to many processes simultaneously.  ...  In this paper, we present a method of code cache sharing among processes for dynamic tools operating on native applications.  ...  our coarse-grained strategy more difficult to achieve, allowing the fine-grained management to handle all of the corner cases.  ... 
doi:10.1145/1346256.1346265 dblp:conf/vee/BrueningK08 fatcat:rabu377dubfbjnpev6tx7vci4i

Scalable security for large, high performance storage systems

Andrew W. Leung, Ethan L. Miller
2006 Proceedings of the second ACM workshop on Storage security and survivability - StorageSS '06  
Combining and caching client verifications reduces client latencies and workload because metadata and data requests are more frequently serviced by cached capabilities.  ...  Additionally, our approach improves MDS performance considerably, serving over 99% of all file access requests with cached capabilities.  ...  We would also like to thank Martín Abadi and all of the members of the Storage Systems Research Center, whose support and advice helped guide us through this work.  ... 
doi:10.1145/1179559.1179565 dblp:conf/storagess/LeungM06 fatcat:sapzckrrzrdhjchju7puahlpv4

Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine

Keun Sup Shim, Mieszko Lis, Myong Hyon Cho, Ilia Lebedev, Srinivas Devadas
2013 2013 IEEE 31st International Conference on Computer Design (ICCD)  
In this paper, we describe the design choices made in the EM² chip as well as our choice of design methodology, and discuss how they combine to achieve design simplicity and verification efficiency.  ...  Even though EM² is a fairly large design-110 cores using a total of 357 million transistors-the entire chip design and implementation process (RTL, verification, physical design, tapeout) took only 18  ...  To leverage this locality, EM² complements the remote cache access mechanism with fine-grained hardware-level thread migration [16] .  ... 
doi:10.1109/iccd.2013.6657037 dblp:conf/iccd/ShimLCLD13 fatcat:mgif6qbbn5cmzmpy2ct65jdwte

A Technique Preventing Code Reuse Attacks Based on RISC Processor

Yang LI, Yang LI, Jun-wei LI
2018 DEStech Transactions on Computer Science and Engineering  
This system based on RISC processors can defend code reuse attacks, as well as prevent high overhead caused by the implementation of software fine-grained control flow integrity technology.  ...  of ROP, JOP and COOP.  ...  At the same time, the tag table is stored in physical memory, and a hardware tag cache module is added, so that fine-grained control flow integrity technology can be implemented to support full-flow hardware  ... 
doi:10.12783/dtcse/ccnt2018/24682 fatcat:5ahcjiqvofdhffo73664ezbvla

Supporting highly-decoupled thread-level redundancy for parallel programs

M. Wasiur Rashid, Michael C. Huang
2008 High-Performance Computer Architecture  
The increasing prevalence of multi-core architectures makes coarse-grain threadlevel redundancy (TLR) very attractive.  ...  One of the main design goals is to support a large number of unverified instructions, so that long latencies in verification can be easily tolerated.  ...  At best, it is cumbersome to disable fine-grain circuit-level redundancy once it is in-place.  ... 
doi:10.1109/hpca.2008.4658655 dblp:conf/hpca/RashidH08 fatcat:5yz3jejqezfq5njrgf6a6a6gha

Preliminary design of the SAFE platform

André DeHon, Sumit Ray, Olin Shivers, Jonathan M. Smith, Gregory Sullivan, Ben Karel, Thomas F. Knight, Gregory Malecha, Benoît Montagu, Robin Morisset, Greg Morrisett, Benjamin C. Pierce (+1 others)
2011 Proceedings of the 6th Workshop on Programming Languages and Operating Systems - PLOS '11  
We sketch the current state of the design and discuss several of these choices.  ...  Though the project is still at an early stage, we have assembled a set of basic architectural choices that we believe will yield a high-assurance system.  ...  , data, and instructions, and information-flow tracking via fine-grained tagging.  ... 
doi:10.1145/2039239.2039245 dblp:conf/sosp/DeHonKKMMMMPPRS11 fatcat:3zbmz6v65rbm7aw3gtbvr4yukm

Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach

Xiaowei Li, Guihai Yan, Jing Ye, Ying Wang
2018 Science China Information Sciences  
Section 4 details the major design components of FTOC, followed by the evaluation results in Section 5. Section 6 discusses three far-reaching implications of the FTOC paradigm.  ...  verification blind spots, and improving the chip yield.  ...  Fine-grained cache failures can be cured with conventional error correction or bit/row/column replacement.  ... 
doi:10.1007/s11432-017-9290-4 fatcat:3mwg4l5pyrashe6het5rlsnlue

Practical Context-Sensitive CFI

Victor van der Veen, Dennis Andriesse, Enes Göktaş, Ben Gras, Lionel Sambuc, Asia Slowinska, Herbert Bos, Cristiano Giuffrida
2015 Proceedings of the 22nd ACM SIGSAC Conference on Computer and Communications Security - CCS '15  
Current Control-Flow Integrity (CFI) implementations track control edges individually, insensitive to the context of preceding edges.  ...  We present PathArmor, a binary-level CCFI implementation which tracks paths to sensitive program states, and defines the set of valid control edges within the state context to yield higher precision than  ...  to the coarse-grained and fine- grained versions of CCFI (respectively, +245% and +53% geometric mean).  ... 
doi:10.1145/2810103.2813673 dblp:conf/ccs/VeenAGGSSBG15 fatcat:z472k2nzdjg33no7nqjcbhwjaa

Cache Coherence Protocols in Distrubted Systems

Hanan Shukur, Subhi Zeebaree, Rizgar Zebari, Omar Ahmed, Lailan Haji, Dildar Abdulqader
2020 Journal of Applied Science and Technology Trends  
Also, cache coherent protocols have a great task for keeping the interconnection of caches in a multiprocessor environment.  ...  The major challenge of shared memory devices is to maintain the cache coherently.  ...  They aimed to enable fine grained parallelism by optimizing the overhead of communication through coordinating cache coherence protocol.  ... 
doi:10.38094/jastt1329 fatcat:si6jqibdnbfufnthjsyq5gmpre

Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor

Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay S. Lee
1998 SIGARCH Computer Architecture News  
With a three-processor implementation of the MAP, fine-grain speedups of 1.2-2.1 are demonstrated on a suite of applications.  ...  Fine-grain threads fill the parallelism gap between these extremes by enabling tasks with run lengths as small as 20 cycles.  ...  Thanks also to the Spectrum Design Services group at Cadence Design Systems for their contributions to the physical design of the MAP chip.  ... 
doi:10.1145/279361.279399 fatcat:neuvlxywjvfpfgpiuqostf5kci


Seong-Lyong Gong, Minsoo Rhu, Jungrae Kim, Jinsuk Chung, Mattan Erez
2015 Proceedings of the 48th International Symposium on Microarchitecture - MICRO-48  
We propose a novel memory protection scheme called CLEAN (Chipkill-LEvel reliable and Access granularity Negotiable), which enables us to balance the contradicting demands of fine-grained (FG) access and  ...  By enforcing coarse-grained (CG) access, we can get only the advantage of higher protection comparable to Chipkill instead of achieving the adaptive access granularity together.  ...  ACKNOWLEDGEMENTS The authors acknowledgement the support of the National Science Foundation under Grant #0954107, which partially funded this reasearch.  ... 
doi:10.1145/2830772.2830799 dblp:conf/micro/GongRKCE15 fatcat:mjjew46fwzgv3iuilrlfnjmkki

The Wisconsin Wind Tunnel project

Mark D. Hill, James R. Larus, David A. Wood
1994 SIGARCH Computer Architecture News  
This document lists contributors to the Wisconsin Wind Tunnel Project, gives a brief description of the project, and presents references and abstracts to its principal papers, including how to obtain them  ...  Fine-grain messaging provides the short, low-latency messages required to implement cache coherence protocols and support fine-grain parallelism.  ...  Fine-grain Access Control for Distributed Shared Memory.  ... 
doi:10.1145/192537.192543 fatcat:rvtgkgeonnba3cdbociaiglrdq
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