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Fifteen Years of Formal Property Verification in Intel [chapter]

Limor Fix
Lecture Notes in Computer Science  
Originally intended for the analysis of concurrent software, model checking was first used in hardware verification.  ...  The abstraction methods developed for hardware verification however have been a stepping stone for the new generation of software verification tools including SLAM, BLAST, and MAGIC which focus on control-intensive  ...  From Hardware Verification to Software Verification The last several years have seen the development of a new generation of software model checkers such as SLAM, BLAST and MAGIC [1, 14, 4] which are  ... 
doi:10.1007/978-3-540-69850-0_8 fatcat:xyzf4uy7z5aozlelz7igs2xzk4

FACT: A Probabilistic Model Checker for Formal Verification with Confidence Intervals [chapter]

Radu Calinescu, Kenneth Johnson, Colin Paterson
2016 Lecture Notes in Computer Science  
As such, FACT can prevent invalid decisions in the construction and analysis of systems, and extends the applicability of quantitative verification to domains in which unknown estimation errors are unacceptable  ...  We introduce FACT, a probabilistic model checker that computes confidence intervals for the evaluated properties of Markov chains with unknown transition probabilities when observations of these transitions  ...  Introduction The development of quantitative verification [8, 11] over the past fifteen years represents one of the most prominent recent advances in system modelling and analysis.  ... 
doi:10.1007/978-3-662-49674-9_32 fatcat:3eml6tjviff5tk6oqr5iwycx5y

Engineering Sufficiently Secure Computing

Brian Witten
2006 Proceedings of the Computer Security Applications Conference  
Cryptographic separation protects information in transmission and storage. Formally proven properties of separation kernel based secure virtualization can bound risk for information in processing.  ...  We propose an architecture of four complimentary technologies increasingly relevant to a growing number of home users and organizations: cryptography, separation kernels, formal verification, and rapidly  ...  in scalability of formal verification.  ... 
doi:10.1109/acsac.2006.25 dblp:conf/acsac/Witten06 fatcat:tclioh6qkna6vkuhzsflauh2sm

A journey in Computational Logic in Italy

Matteo Baldoni, Cristina Baroglio
2011 Intelligenza Artificiale  
The fifteen selected articles, included in the special issue, describe some of the most relevant recent experiences and some of the most promising investigations that were (and are being) carried on in  ...  The aim of this special issue is to witness this effort. As such, it complements the survey of the first twenty-five years of existence of GULP, edited by Agostino Dovier and Enrico Pontelli in 2010.  ...  Nicola Olivetti, Viviana Patti, Maria Luisa Sapino, and Piero Torasso for their encouragement and support, Oliviero Stock and the editorial board the Intelligenza Artificiale journal for the opportunity of  ... 
doi:10.3233/ia-2011-0005 dblp:journals/ia/BaldoniB11 fatcat:6icuqs46ibh3jnnnijug3iormy

Formalizing hardware/software interface specifications

Juncao Li, Fei Xie, Thomas Ball, Vladimir Levin, Con McGarvey
2011 2011 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011)  
We have detected fifteen issues in four English specifications.  ...  Furthermore, our formal specifications are readily useful as the test harnesses for co-verification, which has discovered twelve real bugs in five industrial driver programs.  ...  This research received financial support from National Science Foundation of the United States (Grant #: 0916968).  ... 
doi:10.1109/ase.2011.6100048 dblp:conf/kbse/LiXBLM11 fatcat:2iigidstfje43ed4kiptkm6744

The empirical status of the formal operations

R J Ross
1974 Adolescence  
Recently, Piaget (1972) advanced the notion that in some circumstances the appearance of the formal operations may be delayed to the years be- tween fifteen and twenty.  ...  The Jackson study cited above evidenced a similar drop in percentages with the III-B criterion (thirteen-year-olds = 4%, fifteen-year-olds = 10%).  ... 
pmid:4429029 fatcat:4slinardzff5ve4m4ndhlxt3um

An Ultra-Lightweight Mutual Authentication Scheme for Smart Grid Two-way Communications

Saeed Aghapour, Masoud Kaveh, Mohammad Reza Mosavi, Diego Martin
2021 IEEE Access  
gateways in recent years.  ...  It is well established that the efficiency, safety, flexibility, and reliability of the power grid is improved by utilization of information and communication technology (ICT) in smart grid.  ...  FORMAL SECURITY ANALYSIS In this section, we bring a formal proof to make sure that any adversary as claimed in section III cannot achieve the communicated secret parameters of the protocol.  ... 
doi:10.1109/access.2021.3080835 fatcat:j4djudwhcnglhevocid6eapxra

Platform-Based Design Methodology and Modeling for Aircraft Electric Power Systems [article]

Pierluigi Nuzzo, John Finn, Mohammad Mozumdar, Alberto Sangiovanni-Vincentelli
2013 arXiv   pre-print
State-machine diagrams enable verification of the control protocol at a high level of abstraction, while lowerlevel hybrid models, implemented in Simulink, are used to verify properties related to physical  ...  In PBD, design space exploration is carried out as a sequence of refinement steps from the initial specification towards a final implementation, by mapping higher-level behavioral models into a set of  ...  INTRODUCTION The advent of high capability, reliable power electronics together with powerful embedded processors has enabled, over the last fifteen years, an increasing amount of "electrification" of  ... 
arXiv:1311.6092v1 fatcat:6iyodyvnqngdzn5uoyb64qsyme

HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms

Liang-Bi CHEN, Jiun-Cheng JU, Chien-Chou WANG, Ing-Jer HUANG
2010 IEICE transactions on information and systems  
They are still lack of an efficient bus protocols verification environment such as FPGA-level or chip-level.  ...  mechanisms: an error reference table (ERT) and a windowed trace buffer, to shorten verification time.  ...  [10] also used formal modeling and symbolic check to verify Intel Itanium processor bus functionality. Formal modeling and symbolic check is the one of most popular topics in this domain.  ... 
doi:10.1587/transinf.e93.d.2100 fatcat:dzordpg3qveptpofwttp55yp5m

Front Matter

2021 2021 IEEE Microelectronics Design & Test Symposium (MDTS)  
The symposium provides a forum for discussions on the latest issues in the design and test of microelectronics, broadening our scope from previous years.  ...  MDTS's four paper sessions included fifteen peer-reviewed research and industry papers, eight of which were student papers.  ...  Formal Verification (Marvell) Abstract: Logical Equivalence Formal Verification (LEFV) or Logical Equivalence check (LEC) has been used mainly in ASIC design to verify functional logic equivalence, not  ... 
doi:10.1109/mdts52103.2021.9476087 fatcat:niu4nujwobcfxnki6xfjdf7x34

A Nonexistence Certificate for Projective Planes of Order Ten with Weight 15 Codewords [article]

Curtis Bright, Kevin Cheung, Brett Stevens, Dominique Roy, Ilias Kotsireas, Vijay Ganesh
2020 arXiv   pre-print
In particular, we show that there exist no projective planes of order ten that generate codewords of weight fifteen, a result first shown in 1973 via an exhaustive computer search.  ...  Using techniques from the fields of symbolic computation and satisfiability checking we verify one of the cases used in the landmark result that projective planes of order ten do not exist.  ...  In contrast, we have given a simple translation of properties of a weight fifteen codeword into Boolean logic and have shown that these properties are sufficient to prove that such a codeword cannot exist  ... 
arXiv:1911.04032v2 fatcat:4kil754abjdydh4bhl2e4nllrm

A Model-Based Testing Framework for Automotive Embedded Systems

Raluca Marinescu, Mehrdad Saadatmand, Alessio Bucaioni, Cristina Seceleanu, Paul Pettersson
2014 2014 40th EUROMICRO Conference on Software Engineering and Advanced Applications  
To enjoy the fully-fledged advantages of reasoning, EAST-ADL models could benefit from a component-aware analysis framework that provides, ideally, both verification and model-based test-case generation  ...  In this paper, we present a methodology for code validation, starting from EAST-ADL artifacts.  ...  RELATED WORK Model-based testing by model-checking is a technique introduced almost fifteen years ago [15] as an efficient way of using a model-checker to interpret traces as test-cases.  ... 
doi:10.1109/seaa.2014.70 dblp:conf/euromicro/MarinescuSBSP14 fatcat:6yg72o7cljh3beiwtnaha7scre

Towards Practical Verification of Machine Learning: The Case of Computer Vision Systems [article]

Kexin Pei, Yinzhi Cao, Junfeng Yang, Suman Jana
2017 arXiv   pre-print
VeriVis leverage different input space reduction techniques for efficient verification of different safety properties.  ...  VeriVis is able to find thousands of safety violations in fifteen state-of-the-art computer vision systems including ten Deep Neural Networks (DNNs) such as Inception-v3 and Nvidia's Dave self-driving  ...  All these DNNs are considered major breakthroughs in DNN architectures as they improved the state-of-the-art performances during each year of ILSVRC [40] competitions.  ... 
arXiv:1712.01785v3 fatcat:bxln4kg5xfbuzdyvuxsfsj7cqa

Improving Constraint-Based Testing with Dynamic Linear Relaxations

Tristan Denmat, Arnaud Gotlieb, Mireille Ducasse
2007 The 18th IEEE International Symposium on Software Reliability (ISSRE '07)  
In CBT, testing objectives are given under the form of properties to be satisfied by program's input/output.  ...  They dramatically increase the solving capabilities of the solver in the presence of non-linear constraints without compromising the completeness or soundness of the overall CBT process.  ...  Constraint-Based Testing (CBT) was introduced fifteen years ago, in the context of mutation testing [9] , to generate test cases by using constraint solving techniques.  ... 
doi:10.1109/issre.2007.34 dblp:conf/issre/DenmatGD07 fatcat:ap2jicpe4ndjxp4ovjd5jtzxqm

First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

Ezio Bartocci, Yliès Falcone, Borzoo Bonakdarpour, Christian Colombo, Normann Decker, Klaus Havelund, Yogi Joshi, Felix Klaedtke, Reed Milewicz, Giles Reger, Grigore Rosu, Julien Signoles (+3 others)
2017 International Journal on Software Tools for Technology Transfer (STTT)  
The first international Competition on Runtime Verification (CRV) was held in September 2014, in Toronto, Canada, as a satellite event of the 14th international conference on Runtime Verification (RV'14  ...  The event was organized in three tracks: (1) offline monitoring, (2) online monitoring of C programs, and (3) online monitoring of Java programs.  ...  All the authors acknowledge the support of the ICT COST Action IC1402 Runtime Verification beyond Monitoring (ARVI).  ... 
doi:10.1007/s10009-017-0454-5 fatcat:u6hmnzu5tbedtcw7hpjodrgzom
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