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Field programmable port extender (FPX) for distributed routing and queuing
2000
Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00
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ABSTRACT Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial ...
advantage and that copies bear this notice and the full citation on the first page. ...
doi:10.1145/329166.329196
dblp:conf/fpga/LockwoodTT00
fatcat:qb23rrxp6vgobpaykogqvle24e
Field Programmable Port Extender (FPX) User Guide (Version 2.2)
2002
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Follow this and additional works at: Abstract: The Field-programmable Port Extender (FPX) is a general-purpose, reprogrammable platform that performs data processing in Field Programmable Gate Array (FPGAs ...
This manual summarizes how to insert the Field Programmable Port Extender (FPX) into the Washington University Gigabit Switch (WUGS), how to install the NCHARGE control software, how to initialize the ...
The KCPSM The FPX KCPSM Module is a small, active, and reconfigurable processing node for the Field-programmable Port Extender (FPX) using the Layered Protocol Wrappers and the KCPSM. ...
doi:10.7936/k7sj1hz1
fatcat:vniweq5w7jdrxmz67ihujosmda
Automated tools to implement and test Internet systems in reconfigurable hardware
2003
Computer communication review
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Circuits created by the integration tool are deployed into a Field-programmable Port Extender (FPX) platform. ...
Tools have been developed to automatically integrate and test networking systems in reconfigurable hardware. These tools dynamically generate circuits for Field Programmable Gate Arrays (FPGAs). ...
reviewers of this SIGCOMM CCR issue for their helpful comments, and all of the visitors, graduate researchers, and CSE536 and CS536 students that have developed modules for the FPX platform and provided ...
doi:10.1145/956993.957006
fatcat:dos3zx62hjhufmsj2rarfzsc5y
Dynamic hardware plugins: exploiting reconfigurable hardware for high-performance programmable routers
2002
Computer Networks
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The DHP architecture is presented within the context of a programmable router architecture which processes flows in both software and hardware. ...
This paper presents the dynamic hardware plugins (DHP) architecture for implementing multiple networking applications in hardware at programmable routers. ...
The authors would also like to thank Naji Naufel for his contributions to the FPX project. ...
doi:10.1016/s1389-1286(01)00289-4
fatcat:fqvst23iyjagvpnwjagglmuug4
Management and Service Discovery in Satellite and Avionic Networks
2007
2007 IEEE Aerospace Conference
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Low latency communications can be achieved by using a combination of distributed airborne and space-based systems. ...
The overlay network is developed using a Peer-to-Peer Application Programmers Interface (API) called JXTA. Nodes simulate resources requesting and offering several types of video and data services. ...
ONL contains Field Programmable Port Extenders (FPXs) [4] and Smart Port Cards (SPCs) [16] that perform router plug-in functions. ...
doi:10.1109/aero.2007.352808
fatcat:z4apmeb2o5aidpxtafkpxl32mq
Deep packet inspection using parallel bloom filters
2004
IEEE Micro
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Prototype implementation and results We implemented a prototype system in an Xilinx XCV2000E field-programmable gate array (FPGA), using the Field-Programmable Port Extender (FPX) platform. 6 We implemented ...
The analysis shows that an implementation with field-programmable gate arrays (FPGAs) can support multigigabit per second line speeds while scanning for more than 10,000 strings. ...
queuing. ...
doi:10.1109/mm.2004.1268997
fatcat:qm5w2kyq4fcvjnvztm65n3lnby
Intelligent Avionics with Advanced Clustering
2008
IEEE Aerospace Conference. Proceedings
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Massive computation and communication is required for distributed real time MTT. In this paper, the K-means clustering algorithm is used to aggregate redundant tracks. ...
In our approach, we identify similar tracking data to be distributed and send only one copy of the message. ...
The gateway node has the ability to process the data at the network level between when it is received at the input port and routed to the output port. ...
doi:10.1109/aero.2008.4526593
fatcat:ofettazt4vawzfrkvy2r3i7iom
System-on-chip packet processor for an experimental network services platform
GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489)
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This paper describes the design of a system-on-chip Packet Processor for the NSP which performs all core packet processing functions including segmentation and reassembly, packet classification, route ...
The NSP provides an extensible platform for prototyping next-generation network services and applications. ...
ACKNOWLEDGMENTS We would like to thank John DeHart for his invaluable assistance with system verification. We also would like to thank Fred Kuhns for his assistance with system design and integration. ...
doi:10.1109/glocom.2003.1258967
dblp:conf/globecom/TaylorCCDLTT03
fatcat:k6mzhakinfg3pozkdyschj3exm
Design and evaluation of a high-performance dynamically extensible router
Proceedings DARPA Active Networks Conference and Exposition
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It provides an experimental platform for research on programmable networks, protocols, router software and hardware design, network management, quality of service and advanced applications. ...
It supports gigabit links and uses a scalable architecture suitable for supporting hundreds or even thousands of links. ...
Programmable port eXtender (FPX). ...
doi:10.1109/dance.2002.1003483
dblp:conf/dance/KuhnsDKKLPRTPSTW02
fatcat:qgjh25apkjgynj52rcit62zt3m
Dynamic hardware plugins (DHP): exploiting reconfigurable hardware for high-performance programmable routers
2001 IEEE Open Architectures and Network Programming Proceedings. OPENARCH 2001 (Cat. No.01EX484)
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The DHP architecture is presented within the context of a programmable router architecture which processes flows in both software and hardware. ...
This paper presents the Dynamic Hardware Plugins (DHP) architecture for implementing multiple networking applications in hardware at programmable routers. ...
The authors would also like to thank Naji Naufel for his contributions to the FPX project. ...
doi:10.1109/opnarc.2001.916836
fatcat:m542tw3qkjcstfxumijhomp7d4
TCP Processor: Design, Implementation, Operation, and Usage
2004
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It is a hardware circuit designed to perform TCP stream reassembly operations for 8 million bi-directional TCP connections at OC-48 (2.5 Gbps) data rates. ...
It is a hardware circuit designed to perform TCP stream reassembly operations for 8 million bi-directional TCP connections at OC-48 (2.5 Gbps) data rates. ...
Field-programmable Port Extender The Field-programmable Port Extender (FPX) [9] is a research platform which supports the processing of high-speed network traffic with reconfigurable devices. ...
doi:10.7936/k7639n1v
fatcat:fo3uadcymfhwjd7hqgx3lbutja
Techniques for Processing TCP/IP Flow Content in Network Switches at Gigabit Line Rates
2004
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It describes an architecture that simplifies the processing of TCP data streams in these environments and presents a hardware circuit capable of TCP stream processing on multi-gigabit networks for millions ...
It describes an architecture that simplifies the processing of TCP data streams in these environments and presents a hardware circuit capable of TCP stream processing on multi-gigabit networks for millions ...
Field-programmable Port Extender The Field-programmable Port Extender (FPX) [74, 73] is a research platform that supports the processing of high-speed network traffic with reconfigurable devices (Figure ...
doi:10.7936/k7zk5f02
fatcat:2g6nhip54bab7e7hbfricyviei
HAIL: An Algorithm for the Hardware Accelerated Identification of Languages, Master's Thesis, May 2006
2006
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HAIL has been implemented on the Field-programmable Port eXtender (FPX), an open hardware platform developed at Washington University in St. Louis. ...
HAIL has been implemented on the Fieldprogrammable Port eXtender (FPX), an open hardware platform developed at Washington University in St. Louis. ...
HAIL has been implemented on the Field-Programmable Port eXtender (FPX), an open platform developed at Washington University in St. Louis. ...
doi:10.7936/k76d5rc5
fatcat:aq7ek3vwxjhhpgka2g56i43pda
Models, Algorithms, and Architectures for Scalable Packet Classification
2004
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, and a new packet classification algorithm that scales to support high-speed links and large filter sets classifying on additional packet fields. ...
As these searching tasks must be performed for each packet traversing the router, the speed and scalability of the solutions to the route lookup and packet classification problems largely determine the ...
John Lockwood for offering valuable suggestions and insight, supporting a portion of my graduate studies, involving me in the early development of the Field-programmable Port eXtender (FPX), and demonstrating ...
doi:10.7936/k7fq9tzd
fatcat:tb5dig4btzckxmd6veqdqi3vx4
IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application
19th IEEE International Parallel and Distributed Processing Symposium
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On the data path, reconfigurable hardware logic implements time-critical functions for AES encryption and HMAC authentication. ...
In traditional hardware systems, it is often the case that fast hardware modules wait for slow softwares to feed input data and retrieve output data. ...
The design and implementation of the extensible router involves the hard work of other project members: John DeHart, Fred Kuhns and David Zar. ...
doi:10.1109/ipdps.2005.262
dblp:conf/ipps/LuL05
fatcat:z73odssxlzdfxkjw7tppr3sye4
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