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Welcome Message and Committees for NEXTA 2018

2018 2018 IEEE International Conference on Software Testing, Verification and Validation Workshops (ICSTW)  
Gregory Gay and Dr. Mike Papadakis as well as the entire ICST 2018 organsation for their support.  ...  addition, we want to thank our sponsors for the workshop; IEEE Computer Society, as well as the Swedish chapter in Region 8, The Eureka ITEA 3 TESTOMAT Project this time the workshop is funded in Sweden by  ...  -Evaluating Test Data Generation for Untyped Data Structures Using Genetic Algorithms (Ralf Gerlich and Christian Praus) -Feature based testing by using model synthesis, test generation and parameterizable  ... 
doi:10.1109/icstw.2018.00012 fatcat:nyfvdrpghrcajjihfvs7koafzi

Generator based approach for analog circuit and layout design and optimization

A Graupner, R Jancke, R Wittmann
2011 2011 Design, Automation & Test in Europe  
This paper presents a new methodology for layout generation of analog circuits that is based on a modular circuit design and a so-called "executable design flow description".  ...  This is created once manually and allows to describe the layout in a technology independent and parameterizable manner assuring a consistent view of circuit and layout design.  ...  ACKNOWLEDGMENT This work is supported by the German Ministry of Education and Research BMBF under grant number 01M3086.  ... 
doi:10.1109/date.2011.5763267 dblp:conf/date/GraupnerJW11 fatcat:4uaz7rvccnhqbpyaknojyttz4i

A Survey of Test Based Automatic Program Repair

Yuzhen Liu, Long Zhang, Zhenyu Zhang
2018 Journal of Software  
In this paper, we systematically survey the work in mainstream of test-based program repair (TBR) and discuss the properties automatically generated patches should have.  ...  Hence automatic program repair techniques, especially the test-based approaches, have drawn great attentions in recent years.  ...  Prophet [33] ranked and validated generated patches by the similarities with human written patches according to extracted program value features and modification features. Schramm et al.  ... 
doi:10.17706/jsw.13.8.437-452 fatcat:dz3jksehabg2nptmugyuchghqu

Invariant-Based Safety Assessment of FPGA Projects: Conception and Technique

Vyacheslav Kharchenko, Oleg Illiashenko, Vladimir Sklyar
2021 Computers  
The second type of invariants is formed based on an analysis of the specifics of a particular FPGA project and reflects the features of the tasks to be solved, the algorithms that are implemented, the  ...  hardware FPGA chips used, and the computer-aided design tools, etc.  ...  Acknowledgments: This work was supported by the ECHO project, which has received funding from the European Union's Horizon 2020 research and innovation program under the grant agreement no 830943.  ... 
doi:10.3390/computers10100125 fatcat:p2ueangclncxddzoncnji2a4k4

OpenPiton

Jonathan Balkind, Xiaohua Liang, Matthew Matl, David Wentzlaff, Michael McKeown, Yaosheng Fu, Tri Nguyen, Yanqi Zhou, Alexey Lavrov, Mohammad Shahrad, Adi Fuchs, Samuel Payne
2016 ACM SIGOPS Operating Systems Review  
OpenPiton provides a complete verification infrastructure of over 8000 tests, is supported by mature software tools, runs full-stack multiuser Debian Linux, and is written in industry standard Verilog.  ...  , and configurability, alongside an established base of verification tools and supported software.  ...  Acknowledgements This work was partially supported by the NSF under Grants No. CCF-1217553, CCF-1453112, and CCF-1438980, AFOSR under Grant No. FA9550-14-1-0148, and DARPA under Grants No.  ... 
doi:10.1145/2954680.2872414 fatcat:hchc5lc3qvdlharpit6pl5wrau

Limitations and challenges of computer-aided design technology for CMOS VLSI

R.E. Bryant, Kwang-Ting Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J.M. Rabaey, A. Sangiovanni-Vincentelli
2001 Proceedings of the IEEE  
Design technology (DT) is concerned with the automated or semiautomated conception, synthesis, verification, and eventual testing of microelectronic systems.  ...  A second limitation is that the effectiveness of the design process is determined by its context-the design methodologies and flows we employ, and the designs that we essay-perhaps more than by its component  ...  Unfortunately, most existing delay techniques are based on simplified, logic-level models and cannot be directly used to model and test timing defects in high-speed designs that use DSM technologies.  ... 
doi:10.1109/5.915378 fatcat:jocv62sorfbnjp53u7b76j4mdi

A Flexible Software/Hardware Adaptive Network for Embedded Distributed Architectures

Celine Azar
2021 Circuits and Systems An International Journal  
We provide the DMC module in this work and assess SNet performance by executing a large number of test cases.  ...  To design routing pathways among communicating processes, it uses a distributed, adaptive, non-supervised routing method based on the ACO algorithm (Ant Colony Optimization).  ...  By using defined simulation settings and realistic traffic models, we choose an evaluation technique proposed in [24] to extract the features of various routing topologies applied to SNet.  ... 
doi:10.5121/csij.2021.8301 fatcat:j47qdh26anc3jjpmbsqrx66hdq

Antikernel: A Decentralized Secure Hardware-Software Operating System Architecture [chapter]

Andrew Zonenberg, Bülent Yener
2016 Lecture Notes in Computer Science  
We create and verify an FPGA-based prototype of the system.  ...  To make formal verification easier, and improve parallelism, the Antikernel system is highly modular and consists of many independent hardware state machines (one or more of which may be a general-purpose  ...  By breaking up functionality and decentralizing as much as possible we aim to create a platform that allows applications to pick and choose the OS features they wish to use, thus reducing their attack  ... 
doi:10.1007/978-3-662-53140-2_12 fatcat:twdntldmvfa6nmdxdd2oqxycou

System-level modeling of a network switch SoC

JoAnn M. Paul, Christopher P. Andrews, Andrew S. Cassidy, Donald E. Thomas
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
We present the modeling of the high-level design of a next generation network switch from the perspective of a Computer-Aided Design (CAD) team within the larger context of a design team consisting of  ...  an experienced network switch designer and an experienced VLSI hardware designer.  ...  Acknowledgments This work was supported in part by the Pittsburgh Digital Greenhouse, NSF Award EIA-0103706, the General Motors Collaborative Research Lab at CMU, and ST Microelectronics.  ... 
doi:10.1145/581214.581215 fatcat:hssrvh2bwngjtojozriudveaka

System-level modeling of a network switch SoC

JoAnn M. Paul, Christopher P. Andrews, Andrew S. Cassidy, Donald E. Thomas
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
We present the modeling of the high-level design of a next generation network switch from the perspective of a Computer-Aided Design (CAD) team within the larger context of a design team consisting of  ...  an experienced network switch designer and an experienced VLSI hardware designer.  ...  Acknowledgments This work was supported in part by the Pittsburgh Digital Greenhouse, NSF Award EIA-0103706, the General Motors Collaborative Research Lab at CMU, and ST Microelectronics.  ... 
doi:10.1145/581199.581215 fatcat:rq5jx36amvdhfmyp33ygmro3rq

Synthesis of attributed feature models from product descriptions

Guillaume Bécan, Razieh Behjati, Arnaud Gotlieb, Mathieu Acher
2015 Proceedings of the 19th International Conference on Software Product Line - SPLC '15  
As the manual preparation of feature models is a tedious and labour-intensive activity, some techniques have been proposed to automatically generate boolean feature models from product descriptions.  ...  We have performed an empirical evaluation by using both randomized configuration matrices and real-world examples.  ...  Experiments presented in this paper were carried out using the Grid'5000 (see https://www. grid5000.fr).  ... 
doi:10.1145/2791060.2791068 dblp:conf/splc/BecanBGA15 fatcat:4mcfkvbh7jhibdih7zi76g62a4

Agile Autotuning of a Transprecision Tensor Accelerator Overlay for TVM Compiler Stack [article]

Dionysios Diamantopoulos, Burkhard Ringlein, Mitra Purandare, Gagandeep Singh, Christoph Hagleitner
2020 arXiv   pre-print
We propose an overlay (τ-VTA) and an optimization method guided by agile-inspired auto-tuning techniques. We achieve higher performance and faster convergence than state-of-art.  ...  The rapid development of frameworks, models, and precision options challenges the adaptability of such tensor-accelerators since the adaptation to new requirements incurs significant engineering costs.  ...  We further propose the use of the most important features in order to generate an overlay and then continue with auto-tuning.  ... 
arXiv:2004.10854v1 fatcat:i4gkoxo2nbdf5l3wo5cln77lsy

A Feature-Based Classification of Model Repair Approaches

Nuno Macedo, Tiago Jorge, Alcino Cunha
2017 IEEE Transactions on Software Engineering  
This paper proposes a feature-based classification system for model repair techniques, based on an systematic review of previously proposed approaches.  ...  Of the various stages of consistency management, this work focuses on inconsistency fixing in MDE, where such task is embodied by model repair techniques.  ...  ACKNOWLEDGMENT Work financed by the North Portugal Regional Operational Programme (NORTE 2020), under the PORTUGAL 2020 Partnership Agreement, and through the European Regional Development Fund (ERDF)  ... 
doi:10.1109/tse.2016.2620145 fatcat:hreryhhoxzdtva2i2ta7ipcmuq

Adapting compilation techniques to enhance the packing of instructions into registers

Stephen Hines, David Whalley, Gary Tyson
2006 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06  
, code size, and/or execution time when compared to results using a standard optimizing compiler targeting the IRF.  ...  Instruction packing is a recently developed compiler/architectural approach for reducing energy consumption, code size, and execution time by placing the frequently occurring instructions into an Instruction  ...  This research was supported in part by NSF grants EIA-0072043, CCR-0208892, CCR-0312493, CCF-0444207, and CNS-0615085.  ... 
doi:10.1145/1176760.1176768 dblp:conf/cases/HinesWT06 fatcat:ums24p5apjemlk3efw3qythaey

NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

D. Bertozzi, A. Jalabert, Srinivasan Murali, R. Tamhankar, S. Stergiou, L. Benini, G. De Micheli
2005 IEEE Transactions on Parallel and Distributed Systems  
The NetChip design flow is used to model several video and network applications.  ...  The ×pipesCompiler uses the ×pipes library, which consists of highly parameterizable network building blocks that can be tuned and composed at design time to generate the chosen topology.  ...  The components are highly parameterizable and provide reliable and latency insensitive operation. They represent the core of the NoC synthesis flow illustrated in this paper.  ... 
doi:10.1109/tpds.2005.22 fatcat:fe5adt3herhk3g6j6lo5i7bkm4
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