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Feasible set functions have small circuits

Arnold Beckmann, Sam Buss, Sy-David Friedman, Moritz Müller, Neil Thapen
2018 Computability - The Journal of the Assosiation  
Let g( a, b, x) and h( a, b) be functions from sets to sets.  ...  The second is our main result: the CRSF functions are shown to be precisely the functions computed by a class of uniform, infinitary, Boolean circuits.  ...  . / Feasible set functions have small circuits  ... 
doi:10.3233/com-180096 fatcat:exngvdxcyvfexko562thvw37ia

Investigations on the Optimal Support Vector Machine Classifiers for Predicting Design Feasibility in Analog Circuit Optimization

Jiho Lee, Jaeha Kim
2015 JSTS Journal of Semiconductor Technology and Science  
boundaries of most circuit designs.  ...  For instance, the higher γ is good for detailed modeling and the higher C is good for rejecting noise in the training set.  ...  On the other hand, the penalty parameter is found to have negligible influence because the training samples collected from circuit simulations have little noise and the feasible region boundaries formed  ... 
doi:10.5573/jsts.2015.15.5.437 fatcat:gvnm3huw4ngkfnpapjjfanfpw4

Yield model characterization for analog integrated circuit using Pareto-optimal surface

Sawal Ali, Reuben Wilcock, Peter Wilson, Andrew Brown
2008 2008 15th IEEE International Conference on Electronics, Circuits and Systems  
A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front.  ...  Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield.  ...  The approach can be applied to any circuit topology and enjoys reduced computational overhead due to only focusing the yield simulation on a small feasible region.  ... 
doi:10.1109/icecs.2008.4675065 dblp:conf/icecsys/AliWWB08 fatcat:gs23dyqwfzbilfjc35nng3rhki

A combined feasibility and performance macromodel for analog circuits

Mengmeng Ding, Ranga Vemuri
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
functional or performance constraints considered.  ...  On the other hand, these requirements can cause a large percentage of functionally incorrect designs in the design space and thus results in a sparse feasible design space.  ...  Device size ranges and functional constraints are useful in defining the feasible design space for they ensure the correct behavior of certain circuit [14] .  ... 
doi:10.1145/1065579.1065600 dblp:conf/dac/DingV05 fatcat:cccwe2dldrg5zdllwauht3opee

A combined feasibility and performance macromodel for analog circuits

M. Ding, R. Vemuri
2005 Proceedings. 42nd Design Automation Conference, 2005.  
functional or performance constraints considered.  ...  On the other hand, these requirements can cause a large percentage of functionally incorrect designs in the design space and thus results in a sparse feasible design space.  ...  Device size ranges and functional constraints are useful in defining the feasible design space for they ensure the correct behavior of certain circuit [14] .  ... 
doi:10.1109/dac.2005.193774 fatcat:rwccknbpu5fsbougwcnrv7m77m

Approximation Limitations of Pure Dynamic Programming

Stasys Jukna, Hannes Seiwert
2020 SIAM journal on computing (Print)  
Tropical circuits constitute a rigorous mathematical model for this class of algorithms.  ...  We prove the first, even super-polynomial, lower bounds on the size of tropical (min,+) and (max,+) circuits approximating given optimization problems.  ...  The boolean function defined by the family of feasible solutions of the assignment problem is the boolean permanent function which, as proved by Razborov [26] , requires monotone boolean circuits of size  ... 
doi:10.1137/18m1196339 fatcat:sydprgbzpvf2tkuzfh47vafd7i

Technology mapping for large complex PLDs

Jason Helge Anderson, Stephen Dean Brown
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
Our algorithm produces circuits that require up to 90% fewer logic blocks than the circuits produced by a recently-published algorithm.  ...  We describe an approach that allows existing multi-level synthesis techniques [13] to be adapted to produce circuits that are well-suited for implementation in CPLDs.  ...  Each node in the DAG represents a single logic function in the circuit; the edges in the DAG represent dependencies between logic functions.  ... 
doi:10.1145/277044.277220 dblp:conf/dac/AndersonB98 fatcat:pj6cqzowencl5mw72lci4t6jwi

Duality of sum of nonnegative circuit polynomials and optimal SONC bounds [article]

Dávid Papp
2019 arXiv   pre-print
The quality of the SONC bound depends on the circuits used in the computation, but finding the set of circuits that yield the best attainable SONC bound among the astronomical number of candidate circuits  ...  Our proof, based on convex programming duality, removes the nondegeneracy assumption and motivates an algorithm that generates an optimal set of circuits and computes the corresponding SONC bound in a  ...  If for any α such a circuit does not exist, then (3) trivially does not have a feasible solution, and f + c does not have a SONC bound.  ... 
arXiv:1912.04718v1 fatcat:fes5gx4p6vfwbkmrgocgtrobli

Parameterized Macromodeling for Analog System-Level Design Exploration

Jian Wang, Xin Li, Lawrence T. Pileggi
2007 Proceedings - Design Automation Conference  
In this paper we propose a novel parameterized macromodeling technique for analog circuits.  ...  Unlike traditional macromodels that are only extracted for a small variation space, our proposed approach captures a significantly larger analog design space to facilitate system-level design exploration  ...  The hyperplane is then defined as 0 = 3) Global model fitting We assume that we have in total q small partitions.  ... 
doi:10.1109/dac.2007.375299 fatcat:dnhxee5dvrd53jkar3g3chgx24

Parameterized macromodeling for analog system-level design exploration

Jian Wang, Xin Li, Lawrence T. Pileggi
2007 Proceedings - Design Automation Conference  
In this paper we propose a novel parameterized macromodeling technique for analog circuits.  ...  Unlike traditional macromodels that are only extracted for a small variation space, our proposed approach captures a significantly larger analog design space to facilitate system-level design exploration  ...  The hyperplane is then defined as 0 = 3) Global model fitting We assume that we have in total q small partitions.  ... 
doi:10.1145/1278480.1278711 dblp:conf/dac/WangLP07 fatcat:lb4xxasyefhqzh2szpg3rpwy4u

Small Extended Formulation for Knapsack Cover Inequalities from Monotone Circuits [article]

Abbas Bazzi and Samuel Fiorini and Sangxia Huang and Ola Svensson
2016 arXiv   pre-print
In particular, our LP is based on O(^2 n)-depth monotone circuits with fan-in 2 for evaluating weighted threshold functions with n inputs, as constructed by Beimel and Weinreb.  ...  Our construction is inspired by a connection between extended formulations and monotone circuit complexity via Karchmer-Wigderson games.  ...  In that case the threshold function (and its truncations) can simply be written as the majority function on O( i s i ) input bits and, as such functions have monotone circuits of fan-in 2 of logarithmic  ... 
arXiv:1609.03737v2 fatcat:af2ajlud7zafxi7bmwy5n4q76i

Certifying polynomials for AC^0(parity) circuits, with applications

Swastik Kopparty, Srikanth Srinivasan, Marc Herbstritt
2012 Foundations of Software Technology and Theoretical Computer Science  
This also implies a separation between randomized AC 0 [⊕] circuits of linear size and deterministic AC 0 [⊕] circuits of near-linear size.  ...  This implies a separation between the power of AC 0 [⊕] circuits of nearlinear size and uniform AC 0 [⊕] (and even AC 0 ) circuits of polynomial size.  ...  Acknowledgements We would like to thank Albert Atserias for asking us about the tradeoff between degree and error for approximating polynomials for AC 0 [⊕] circuits.  ... 
doi:10.4230/lipics.fsttcs.2012.36 dblp:conf/fsttcs/KoppartyS12 fatcat:gtjbqrvrmfb6le2gnsbxplxtqa

Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring

Stephen M. Plaza, Igor L. Markov, Valeria M. Bertacco
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the specified performance objectives  ...  By not having a completely specified function, we facilitate multiple feasible implementations.  ...  In logic rewriting, the quality of different functionally equivalent implementations for a small logic block in a circuit is assessed.  ... 
doi:10.1109/tcad.2008.2006156 fatcat:ewqzcfghtfcxrlzvwl2q4ueg6q

Optimizing non-monotonic interconnect using functional simulation and logic restructuring

Stephen M. Plaza, Igor L. Markov, Valeria Bertacco
2008 Proceedings of the 2008 international symposium on Physical design - ISPD '08  
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the specified performance objectives  ...  By not having a completely specified function, we facilitate multiple feasible implementations.  ...  In logic rewriting, the quality of different functionally equivalent implementations for a small logic block in a circuit is assessed.  ... 
doi:10.1145/1353629.1353653 dblp:conf/ispd/PlazaMB08 fatcat:r3byurg6r5axvhnp4v6o7qdloq

Support vector machines for analog circuit performance representation

F. De Bernardinis, M. I. Jordan, A. Sangiovanni Vincentelli
2003 Proceedings of the 40th conference on Design automation - DAC '03  
This function is usually evaluated through simulations and its range defines the feasible performance space of the circuit.  ...  In abstract terms, an analog circuit maps a set of input design parameters to a set of performance figures.  ...  For this reason, any second-order physical effect may have a significant impact on function and performance of an analog circuit.  ... 
doi:10.1145/775832.776074 dblp:conf/dac/BernardinisJS03 fatcat:fduucmxqdbeuxa5xvwl67lovrq
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