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Efficient Majority Logic Fault Detection with Difference-Set Codes for Memory Applications

B. Arun Kumar
2013 IOSR Journal of Electronics and Communication Engineering  
Minimum distances for EG codes are also reasonably good and can be derived analytically. memory error correction code has been implemented using pipelined cyclic corrector where majority logic gate determined  ...  the error .LDPC soft error decoding is also implemented for the same memory error detection and correction comparison of the results are done .as the majority gate can detect only upto 2 error the extending  ...  Efficient Majority Logic Fault Detection with Difference-Set Codes for Memory Applications www.iosrjournals.org  ... 
doi:10.9790/2834-0827178 fatcat:j7lexy4sw5d5thm6mimtpbgsm4

Fault Secure Encoder and Decoder for Memory Applications

Helia Naeimi, Andre DeHon
2007 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)  
The key novel development is the fault-secure detector (FSD) error-correcting code (ECC) definition and associated circuitry that can detect errors in the received encoded vector despite experiencing multiple  ...  We identify a specific FSD-LDPC code that can tolerate up to 33 errors in each memory word or supporting logic that requires only 30% area overhead for memory blocks of 10 Kbits or larger.  ...  Shalini Gohsh for her valuable reference to EG-LDPCs, and Benjamin Gojman for the discussion leading to the optimized majority gate implementation.  ... 
doi:10.1109/dft.2007.54 dblp:conf/dft/NaeimiD07 fatcat:my6sm7trvvel3pbc4qfv5u5gsi

Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes

Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache
2007 13th IEEE International On-Line Testing Symposium (IOLTS 2007)  
The problem of designing a fault-secure interface between a fault-tolerant RAM memory system and a transmission channel, both protected against errors using cyclic linear error detecting and/or correcting  ...  The main idea relies on using the RAM check bits to control the correct operation of the parallel cyclic code encoder, so that the whole interface has no single point of failure.  ...  It was assumed that the fault-tolerant RAM system with p = 8, 16, and 32 data bits was protected by simple parity code for G 1 (X) and by cyclic Hamming single error correcting codes generated by the polynomials  ... 
doi:10.1109/iolts.2007.32 dblp:conf/iolts/MonteiroPJD07 fatcat:i2gv63bxubh3fp3kxxmqj6gl2e

Optimal Self Correcting Fault Free Error Coding Technique in Memory Operation

Harikishore Kakarla, M Madhavi Latha, Habibulla Khan
2011 International Journal of Computer Science & Information Technology (IJCSIT)  
In this paper an optimal approach for the processing of self correcting logic in faulty condition during coding and decoding operation is developed.  ...  As with the increase in data density the probability of error happening in data transfer has increased the need for error free coding technique is in greater demand.  ...  authorities of KL University, Vijayawada, A.P, India,St.John's College of Engineering and Technology,Kurnool,A.P,India and Jawaharlal Nehru Technological University, College of Engineering, Hyderabad, India for  ... 
doi:10.5121/ijcsit.2011.3305 fatcat:hb3tix7zpnh7ve7wolb7qkigp4

Fault Secure Encoder and Decoder for NanoMemory Applications

H. Naeimi, A. DeHon
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The key novel contribution of this paper is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple.  ...  Using some of the smaller EG-LDPC codes, we can tolerate bit or nanowire defect rates of 10% and fault rates of 10 18 upsets/device/cycle, achieving a FIT rate at or below one for the entire memory system  ...  Ghosh for her valuable reference to EG-LDPCs. This material is based upon work supported by the Department of the Navy, Office of Naval Research.  ... 
doi:10.1109/tvlsi.2008.2009217 fatcat:dgigjcg5w5gdpgds52mokjpfnq

Fault Secure Encoder and Decoder with Clock Gating

N Kapileswar
2012 International Journal of VLSI Design & Communication Systems  
This paper presents circuit design for a low power fault secure encoder and decoder system.  ...  The proposed design uses error correcting codes and ring counter addressing scheme. In the ring counter several new clock gating techniques are proposed to reduce power consumption.  ...  Before decoding the code word, errors should corrected, otherwise the decoded information is not same as the transmitted information.  ... 
doi:10.5121/vlsic.2012.3212 fatcat:h7oyr676lfhbdoa2sspmclmmfa

Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder

Helia Naeimi, Andre DeHon
2007 Proceedings of the Second International Conference on Nano-Networks  
We also present a design to unify the error-correction coding and circuitry used for permanent defect and transient fault tolerance.  ...  Using Euclidean Geometry error-correcting codes (ECC), we identify particular codes which correct up to 8 errors in data words, achieving a FIT rate at or below one for the entire memory system for bit  ...  A code is said to be Cyclic code if for any codeword c, all the cyclic shifts of the codeword are still valid codewords.  ... 
doi:10.4108/icst.nanonet2007.2029 dblp:conf/nanonet/NaeimiD07 fatcat:gds43opd4re6hff7bgoz33b42y

A Brief Review on Soft Errors and LDPC Codes

2016 International Journal of Science and Research (IJSR)  
Many error detection and correction codes have been studied to reduce this error. There are vast classes of such codes; some of them are hamming codes, turbo codes, BCH codes and LDPC codes.  ...  LDPC codes are also used for 10GBase-T Ethernet that transmits data at 10 gigabits per second over twisted pair cable.  ...  Summary The survey on the soft errors and LDPC codes conclude that LDPC codes are one of the best codes for mitigation of soft errors.  ... 
doi:10.21275/v5i6.nov164202 fatcat:ul47qfxukjgwfgc55djxpycu2m

A comparative code study for quantum fault-tolerance [article]

Andrew W. Cross, David P. DiVincenzo, Barbara M. Terhal
2009 arXiv   pre-print
We study a comprehensive list of quantum codes as candidates of codes to be used at the bottom, physical, level in a fault-tolerant code architecture.  ...  We estimate the logical noise rate as a function of overhead at a physical error rate of p_0=1× 10^-4. The Bacon-Shor codes and the Golay code are the best performers in our study.  ...  A construction is called weakly fault-tolerant when, for a code that can correct t errors, sets of s < t locations can be malignant.  ... 
arXiv:0711.1556v2 fatcat:kn6gg7jqbnanng5vgl2p3qdep4

Exploiting Virtual Addressing for Increasing Reliability

Yaman Cakmakci, Oguz Ergin
2014 IEEE computer architecture letters  
Using the encoding scheme to assign VPNs for VAs, it is shown that the system can tolerate soft errors using software with the help of the discussed decoding techniques applied to the page fault handler  ...  A novel method to protect a system against errors resulting from soft errors occurring in the virtual address (VA) storing structures such as translation lookaside buffers (TLB), physical register file  ...  Syndrome Decoding Inside the Page Fault Handler Syndrome decoding is a decoding method widely used for decoding linear block codes.  ... 
doi:10.1109/l-ca.2013.2 fatcat:q7kjspklkfhthh2jc63cndazx4

The gem5 simulator

Nathan Binkert, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, David A. Wood, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi (+4 others)
2011 SIGARCH Computer Architecture News  
Using the encoding scheme to assign VPNs for VAs, it is shown that the system can tolerate soft errors using software with the help of the discussed decoding techniques applied to the page fault handler  ...  A novel method to protect a system against errors resulting from soft errors occurring in the virtual address (VA) storing structures such as translation lookaside buffers (TLB), physical register file  ...  Syndrome Decoding Inside the Page Fault Handler Syndrome decoding is a decoding method widely used for decoding linear block codes.  ... 
doi:10.1145/2024716.2024718 fatcat:4rj2ut4pyve5dacs5ostiwshji

Soft Error Tolerance in Memory Applications

Muhammad Sheikh Sadi, Md. Shamimur, Shaheena Sultana, Golam Mezbah, Kazi Md.
2018 International Journal of Advanced Computer Science and Applications  
Majority logic decodable codes are proved as effective for memory applications because of their ability to correct a massive number of errors.  ...  It works in an efficient manner in case of adjacent errors which is not possible in Majority logic decodable codes (MLD).  ...  [8] proposed a fault-tolerant memory architecture which can tolerate faults both in the storage unit and in the encoder or decoder.  ... 
doi:10.14569/ijacsa.2018.090839 fatcat:6kmntm7z4javhg4bqafn4iwb64

Error-Correcting Codes and Self-Checking Circuits

Pradhan, Stiffler
1980 Computer  
(A "hard core" is that part of a system that cannot tolerate failures, e.g., decoders for error-correcting codes.)  ...  The benefits of error-control codes are demonstrated in the Fault-Tolerant Spaceborne Computer. 4 The FTSC protects all addresses and data by means of various versions of the same (shortened) cyclic  ... 
doi:10.1109/mc.1980.1653527 fatcat:evhwllyaxrg5no45yxtfnpeukm

Flag fault-tolerant error correction, measurement, and quantum computation for cyclic CSS codes [article]

Theerapat Tansuwannont, Christopher Chamberland, Debbie Leung
2019 arXiv   pre-print
We then develop fault-tolerant protocols as well as a family of circuits for flag fault-tolerant error correction and operator measurement, requiring only four ancilla qubits and applicable to cyclic CSS  ...  In this work, we prove some critical properties of CSS codes constructed from classical cyclic codes that enable the construction of a flag fault-tolerant error correction scheme.  ...  Fault-tolerant error correction For t = (d − 1)/2 , an error correction protocol using a distance-d stabilizer code C is t-fault-tolerant if the following two conditions are satisfied: 1.  ... 
arXiv:1803.09758v3 fatcat:i6yzwasqufhirivhf2d7o6gnli

Fault-tolerant Quantum Error Correction on Near-term Quantum Processors using Flag and Bridge Qubits [article]

Lingling Lao, Carmen G. Almudever
2019 arXiv   pre-print
Fault-tolerant (FT) computation by using quantum error correction (QEC) is essential for realizing large-scale quantum algorithms.  ...  We also observe that the Steane code can outperform the distance-3 surface code using flag-bridge error correction.  ...  ACKNOWLEDGMENTS The authors would like to thank Ben Criger for enlightening discussions on this project and feedback on the  ... 
arXiv:1909.07628v1 fatcat:hmvv47ec7rht5jjlsany27gcwa
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