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Fault tolerant electronic system design

Boyang Du, Luca Sterpone
2017 2017 IEEE International Test Conference (ITC)  
Recent researches show that even at sea level, radiation particles can still induce soft errors in electronic systems.  ...  Several solutions exist, acting either on hardware or software: however, they all have to face the high efforts required for designing, manufacturing, testing and qualifying processor-based systems.  ...  tolerant strategies to improve reliability of the system when designing safety-and mission-critical applications.  ... 
doi:10.1109/test.2017.8242080 dblp:conf/itc/DuS17 fatcat:fyonsldknjcutb5p2hiq6brcd4

Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System

Pavel Kubalik, Jiri Kvasnicka, Hana Kubatova
2007 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems  
A Totally Self-Checking analysis of duplex system is supported by experimental results from our proposed FPGA fault simulator, where SEU-fault resistance is observed.  ...  Two FPGAs are used for duplex system design, each including the combination of totally self-checking blocks based on parity predictors to obtain better dependability parameters.  ...  Our solution combines on-line testing design methods with the classical duplex design [6, 8] . It assumes the dynamic reconfiguration of the faulty part of the system after on-line fault detection.  ... 
doi:10.1109/ddecs.2007.4295312 dblp:conf/ddecs/KubalikKK07 fatcat:e77y3mssbrhkvihfxydwmfozbq

A Fault-Aware Toolchain Approach for FPGA Fault Tolerance

Adwait Gupte, Sudhanshu Vyas, Phillip H. Jones
2015 ACM Transactions on Design Automation of Electronic Systems  
These results provide strong evidence that commercial toolchains not designed for the purpose of tolerating faults can still be greatly leveraged in the presence of faults to place and route circuits in  ...  A fault-aware toolchain approach for FPGA fault tolerance.  ...  Design Automation of Electronic Systems, Vol. 20, No. 2, Article 32, Pub. date: February 2015.  ... 
doi:10.1145/2699838 fatcat:74ftgvmzqfesfbh5iu2zpne7de

Fault tolerant control system design with explicit consideration of performance degradation

Youmin Zhang, Jin Jiang
2003 IEEE Transactions on Aerospace and Electronic Systems  
A new approach is proposed for active fault tolerant control systems (FTCS), which allows one to explicitly incorporate allowable system performance degradation in the event of partial actuator fault in  ...  the design process.  ...  INTRODUCTION To design fault tolerant control systems (FTCS), one of the important issues to consider is whether to recover the original system performance/functionality completely or to accept some degree  ... 
doi:10.1109/taes.2003.1238740 fatcat:yq445dn245bt5kkg53dcbqlhta

Module placement for fault-tolerant microfluidics-based biochips

Fei Su, Krishnendu Chakrabarty
2006 ACM Transactions on Design Automation of Electronic Systems  
The placement procedure not only addresses chip area, but also considers fault tolerance, which allows a microfluidic module to be relocated elsewhere in the system when a single cell is detected to be  ...  We focus here on the automated design of "digital" droplet-based microfluidic biochips.  ...  Automation of Electronic Systems,Vol. 11, No. 3, July 2006.  ... 
doi:10.1145/1142980.1142987 fatcat:5eyfxld3hjdalbaan6psajbm34


P. V. Melyushin, E. A. Kazachinskay, S. A. Khmel
2015 Nauka i Tehnika  
The paper considers problems on designing of medical information systems and proposes an approach to creation of a highly reliable automated system for processing electronic medical records on the basis  ...  A mathematical model has been developed for optimal distribution of the files in the network nodes and an experimental investigation of two schemes of medical information systems has been executed in the  ... 
doaj:182714e4f8944d30aaae1d773b1db771 fatcat:46mfo3avcvbvxe2evupdkhscqi

Application-driven co-design of fault-tolerant industrial systems

F. Restrepo-Calle, A. Martinez-Alvarez, H. Guzman-Miranday, F. R. Palomoy, S. Cuenca-As
2010 2010 IEEE International Symposium on Industrial Electronics  
This paper presents a novel methodology for the HW/SW co-design of fault tolerant embedded systems that pursues the mitigation of radiation-induced upset events (which are a class of Single Event Effects  ...  As a case study, we selected a soft-micro (PicoBlaze) widely used in FPGA-based industrial systems, and a fault tolerant version of the matrix multiplication algorithm was developed.  ...  The co-design flow is supported by a hardening platform, which is aimed to develop and evaluate fault tolerant embedded systems.  ... 
doi:10.1109/isie.2010.5637483 fatcat:z4eavmlkonavvi5fbjggzi3odu

Fault-tolerance and noise modelling in nanoscale circuit design

Jahanzeb Anwer, Ahmad Fayyaz, Muhammad M Masud, Saleem F Shaukat, Usman Khalid, Nor H Hamid
2010 2010 International Symposium on Signals, Systems and Electronics  
Fault-tolerance in integrated circuit design has become an alarming issue for circuit designers and semiconductor industries wishing to downscale transistor dimensions to their utmost.  ...  The motivation to conduct research on fault-tolerant design is backed by the observation that the noise which was ineffective in the large-dimension circuits is expected to cause a significant downgraded  ...  system design [4] .  ... 
doi:10.1109/issse.2010.5606936 fatcat:ajrenu5kinb3hh2n3g2tuwy2si

Towards energy-aware software-based fault tolerance in real-time systems

O.S. Unsal, I. Koren, C.M. Krishna
2002 Proceedings of the International Symposium on Low Power Electronics and Design  
In particular, we establish the energy efficiency of Application Level Fault Tolerance (ALFT) over other software-based fault tolerance methods.  ...  In this paper, we focus on the relationship between fault tolerance techniques and energy consumption.  ...  The objective of fault tolerance techniques is to minimize the effects of faults on system operation.  ... 
doi:10.1109/lpe.2002.146724 fatcat:goieuuxfwfcazaqkmsquupqzgy

Using Approximate Computing and Selective Hardening for the Reduction of Overheads in the Design of Radiation-Induced Fault-Tolerant Systems

Alexander Aponte-Moreno, Felipe Restrepo-Calle, Cesar Pedraza
2019 Electronics  
This paper presents a design method of radiation-induced fault-tolerant microprocessor-based systems with lower execution time overheads.  ...  Fault mitigation techniques based on pure software, known as software-implemented hardware fault tolerance (SIHFT), are very attractive for use in COTS (commercial off-the-shelf) microprocessors because  ...  The works that use AC in the design of fault tolerant systems achieve low overheads at the expense of accuracy in the results.  ... 
doi:10.3390/electronics8121539 fatcat:ifdh6oh5bralza523mmvxug2fy

Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint

Yuan Cai, Sudhakar M. Reddy, Bashir M. Al-Hashimi
2007 8th International Symposium on Quality Electronic Design (ISQED'07)  
In this paper we address the problem of reducing the energy consumption in distributed embedded systems associated with time-constraints and equipped with fault-tolerant techniques.  ...  A greedy heuristic is presented to reduce the energy during task mapping and fault tolerance policy assignment. Fault tolerance is achieved through task re-execution and replication.  ...  Problem Formulation There are three issues to be considered in fault tolerant embedded systems design. 1.  ... 
doi:10.1109/isqed.2007.137 dblp:conf/isqed/CaiRA07 fatcat:mcsdbn5t4ffctiira2zrtbydny

Synthesis of fault-tolerant embedded systems with checkpointing and replication

V. Izosimov, P. Pop, P. Eles, Zebo Peng
2006 Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)  
We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications.  ...  Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that transient faults are tolerated  ...  Fault-Tolerant System Design In this paper, by policy assignment we denote the decision whether a certain process should be checkpointed or replicated.  ... 
doi:10.1109/delta.2006.83 dblp:conf/delta/IzosimovPEP06 fatcat:ebonl73lvbgu7jp5eqzvzphkxe

A user-level library for fault tolerance on shared memory multicore systems

Hamid Mushtaq, Zaid Al-Ars, Koen Bertels
2012 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)  
We have designed a library for multicore processing, that can make a multithreaded user-level application fault tolerant by simple modifications to the code.  ...  However, the abundant extra processing resources of a multicore system can be exploited to provide fault tolerance by using redundant execution.  ...  CONCLUSION In this paper, we described the design and implementation of a user-level library for fault tolerance of multithreaded user-level applications running on shared memory multicore systems.  ... 
doi:10.1109/ddecs.2012.6219071 dblp:conf/ddecs/MushtaqAB12 fatcat:25bj6d6jzne4bhjibvn6vvywcy

Towards energy-aware software-based fault tolerance in real-time systems

Osman S. Unsal, Israel Koren, C. Mani Krishna
2002 Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02  
In particular, we establish the energy efficiency of Application Level Fault Tolerance (ALFT) over other software-based fault tolerance methods.  ...  In this paper, we focus on the relationship between fault tolerance techniques and energy consumption.  ...  The objective of fault tolerance techniques is to minimize the effects of faults on system operation.  ... 
doi:10.1145/566408.566442 dblp:conf/islped/UnsalKK02 fatcat:kj6go7qfdzao5g3zmstn5ne5la

Automated Support for the Design and Validation of Fault Tolerant Parameterized Systems: a case study

Francesco Alberti, Silvio Ghilardi, Elena Pagani, Silvio Ranise, Gian Paolo Rossi
2011 Electronic Communications of the EASST  
We propose a methodology to use the infinite state model checker MCMT, based on Satisfiability Modulo Theory techniques, for assisting in the design of fault tolerant algorithms.  ...  Integrating MCMT in the design of fault tolerant algorithms. We propose the following methodology for the design of parametric and fault tolerant algorithms (see also Figure 1 ).  ...  Fault tolerant algorithms in MCMT Several fault tolerant algorithms are described as systems executing a series of "rounds" (see, e.g., [10] ).  ... 
doi:10.14279/tuj.eceasst.35.543 dblp:journals/eceasst/AlbertiGPRR10 fatcat:waqfmk4i3ncjjd7sje7f2by25a
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