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Fault Tolerant Algorithms for a Linear Array with a Reconfigurable Pipelined Bus System [chapter]

Anu G. Bourgeois, Jerry L. Trahan
2000 Lecture Notes in Computer Science  
Recently, many models using recon gurable optically pipelined buses have been proposed in the literature. All algorithms developed for these models assume that a healthy system is available.  ...  We present some fundamental algorithms that are able to tolerate up to N=2 faults on an N -processor LARPBS one particular optical model.  ...  Structure of a Linear Array with a Recon gurable Pipelined Bus System LARPBS.  ... 
doi:10.1007/3-540-45591-4_144 fatcat:f6z2rm3qsnao7mm2vb6x4gm45m

Constant time fault tolerant algorithms for a linear array with a reconfigurable pipelined bus system

Anu G. Bourgeois, Yi Pan, Sushil K. Prasad
2005 Journal of Parallel and Distributed Computing  
The only previous work in this area considers faulty processors or hardware for an N-processor linear array with a reconfigurable pipelined bus system (LARPBS), resulting in fault tolerant algorithms that  ...  There is some fault tolerance work for reconfigurable models with electrical buses [4] , however at this time, the only work to have addressed the issue of fault tolerance for any of the optically pipelined  ...  As a result, researchers have proposed several models based on pipelined optical buses as practical parallel computing platforms including the linear array with a reconfigurable pipelined bus system (LARPBS  ... 
doi:10.1016/j.jpdc.2004.11.002 fatcat:qwagq3ms65avha4h4twzrfz4bm

A Pipelined Fault Tolerant Architecture for Real time DSP Applications

Ahmad Falih Mahmood
2008 Al-Rafidain Engineering Journal  
The fault tolerance provisions in the system, have to incorporate mechanisms to detect and localize errors as well as mechanisms to reconfigure the system (to isolate faulty nodes), and to recover from  ...  Fault tolerance in highly parallel processing systems is important in order to achieve high dependability and sustained high performance computing.  ...  ---"Constant time fault tolerant algorithms for a linear array with a reconfigurable pipelined bus system", J. Parallel Distrib.  ... 
doi:10.33899/rengj.2008.44737 fatcat:6g6zpaz6v5fl5mpujlwdklrcru

Optimal matrix multiplication on fault-tolerant VLSI arrays

P.J. Varman, I.V. Ramakrishnan
1989 IEEE transactions on computers  
In this paper, we present a collinear VLSI array that retains all the desirable fault-tolerance characteristics of Diogenes designs but avoids the degradation in throughput (caused by a lower system clock  ...  While possessing attractive mechanisms for fault-tolerant implementations, Diogenes designs of two-dimensional (2-D) arrays require more area than a two-dimensional implementation and result in long wires  ...  CONCLUDING REMARKS In this paper, we have developed a fault-tolerant array for matrix multiplication that explicitly incorporates mechanisms for easy testability and reconfigurability.  ... 
doi:10.1109/12.16505 fatcat:m3usqgfthrchxfjwokj33bdela

Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems

I. Koren, D.K. Pradhan
1986 Proceedings of the IEEE  
Fault tolerance in these VLSl processor arrays is of real practical significance; it provides for much-needed reliability improvement.  ...  Therefore, we first describe the underlying concepts of fault tolerance at work in these multiprocessor systems.  ...  Algorithms for testing, diagnosis, and reconfiguration need to be developed. Ill.  ... 
doi:10.1109/proc.1986.13532 fatcat:bycl775bmfb27i45ppqy4wykgy

Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis

R. Karri, B. Iyer, I. Koren
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
When phantom redundancy is combined with a concurrent error detection technique, concurrent error detection followed by reconfiguration is automatic.  ...  There is a tight interdependence between reconfiguration of a (faulty) data path and scheduling and operation-to-operator binding tasks during register transfer level synthesis.  ...  Related Research VLSI reconfiguration techniques have been developed to make regular processor arrays tolerant to faults occuring during operation.  ... 
doi:10.1109/tcad.2002.800450 fatcat:cx4737dt5nh6nhgcxx7lv4cgyq

2020 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 28

2020 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs; TVLSI Aug. 2020 Aug. 1925Aug  ...  ., Conflux-An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout; TVLSI Feb. 2020 503-515 Holcomb, D., see 2685-2698 Holcomb, D.E., see 1807-1820 Homayoun  ...  Rahimipour, S., +, TVLSI Oct. 2020 2210-2222 Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based Reconfigurable Designs.  ... 
doi:10.1109/tvlsi.2020.3041879 fatcat:33vb2eia2jfjpog4wei4peq5ge

2D matrix multiplication on a 3D systolic array

Salim Lakhani, Yi Wang, Aleksander Milenković, Veljko Milutinović
1996 Microelectronics Journal  
In this paper we introduce one algorithm for 2D matrix multiplication, using a 3D systolic array.  ...  We analyze advantages and disadvantages of 3D systolic arrays in the context of the analysis algorithm. The analytical work is combined with examples and discussions of relevant details.  ...  One example of such a pipeline is a systolic array to solve a system of linear equations.  ... 
doi:10.1016/0026-2692(95)00008-9 fatcat:2x6k2lhz7vbnrhangymuxzdawe

Design of Reusable Context Pipelining for Coarse Grained Reconfigurable Architecture

P. Murali
2018 International Journal for Research in Applied Science and Engineering Technology  
A typical CGRA requires many processing elements and a configuration cache for reconfiguration of its processing element array. However, such a structure consumes significant area and power.  ...  Therefore, designing cost-effective CGRA has been a serious concern for reliability of CGRA-based embedded systems.  ...  In the case of linear reconfigurable arrays, they support pipelined execution for stream-based applications with static or dynamic reconfiguration.  ... 
doi:10.22214/ijraset.2018.4596 fatcat:6q4jpnj2e5emhgf2m57pfszrti

Cube: A 512-FPGA cluster

Oskar Mencer, Kuen Hung Tsoi, Stephen Craimer, Timothy Todman, Wayne Luk, Ming Yee Wong, Philip Heng Wai Leong
2009 2009 5th Southern Conference on Programmable Logic (SPL)  
With high bandwidth systolic inter-FPGA communication and a flexible programming scheme, the result is a low power, high density and scalable supercomputing machine suitable for various large scale parallel  ...  The machine is made from boards each containing 64 FPGA devices and eight boards can be connected in a cube structure for a total of 512 FPGA devices.  ...  The architecture balances scalability, flexibility and fault tolerance, providing a low cost, high density and versatile research platform for large scale parallel reconfigurable clusters. • A Single Configuration  ... 
doi:10.1109/spl.2009.4914907 fatcat:bkpv4urrena6zexczfkc6vivlq

Recon.gurable Computing and Digital Signal Processing [chapter]

Russell Tessier, Wayne Burleson
2001 Signal Processing and Communications  
This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years.  ...  While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system  ...  Since Splash II is effective in implementing systolic versions of algorithms that require repetitive tasks with data shifted in a linear array, image data can quickly be propagated in a processing pipeline  ... 
doi:10.1201/9780203908068.ch4 fatcat:d6gyesol3bc4rfwc7r4g5wf2ri

A Many-Core Implementation Based on the Reconfigurable Mesh Model

Heiner Giefers, Marco Platzner
2007 2007 International Conference on Field Programmable Logic and Applications  
The reconfigurable mesh is a model for massively parallel computing for which many algorithms with very low complexity have been developed.  ...  These algorithms execute cycles of bus configuration, communication, and constant-time computation on all processing elements in a lock-step.  ...  Another field of application for reconfigurable meshes are fault tolerant systems.  ... 
doi:10.1109/fpl.2007.4380623 dblp:conf/fpl/GiefersP07 fatcat:7zf5khxz2zhvbcuo25aa7mn4ba

FPGA Implementation of On-Chip Network

N Murali Krishna
2018 DJ Journal of Advances in Electronics and Communication Engineering  
Coarse Grained Arrays (CGAs) with run-time re-configurability play a challenging task to design Network on-Chip (NoC) communication systems satisfying the power and area of embedded system.  ...  This paper presents the design of 32 bit UART (Universal Asynchronous Receiver Transmitter) RISC (Reduced Instruction Set Computing) processor with dynamic power management system to minimize power consumption  ...  Several fault errors usually occur in this processor. Therefore modification has to be done in processor design to improve its fault tolerant system thereby mitigating single event upset [14] .  ... 
doi:10.18831/ fatcat:jfgj5g733zbi5mgkfypfzvn6ga

Reconfigurable Architectures [chapter]

Mansureh Shahraki Moghaddam, Jae-Min Cho, Kiyoung Choi
2017 Handbook of Hardware/Software Codesign  
Reconfigurable architecture is a computer architecture combining some of the flexibility of software with the high performance of hardware.  ...  This chapter discusses two major streams of reconfigurable architecture: Field-Programmable Gate Array (FPGA) and Coarse Grained Reconfigurable Architecture (CGRA).  ...  The technique can be used to allow the FPGA to adapt to changing hardware algorithms, improve fault tolerance, and achieve better resource utilization.  ... 
doi:10.1007/978-94-017-7267-9_12 fatcat:bkvbwe3frjhclfdidzburz36ju

An Adaptive Arbitration Technique with 4x4 Mesh Topology for Low Area and High Speed NOC Design

In recent days, On-Chip Communication is a major requirement in modern systems that produce efficient communication with less complexity and high throughput.  ...  In this research work, three different types of arbiter algorithms are used such as priority algorithm, Time Division Multiplexed (TDM) algorithm, and Viterbi algorithm to improve the linearity of the  ...  [16] proposed a path diversity fault-tolerant routing scheme for NoC architecture.  ... 
doi:10.35940/ijitee.e2653.039520 fatcat:2fbh32mjbfgzzntvc6ejh72lji
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