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Scan based methodology for reliable state retention power gating designs

Sheng Yang, Bashir M Al-Hashimi, David Flynn, Saqib Khursheed
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
To the best of our knowledge this is the first study in the area of reliable power gating designs through state monitoring and correction.  ...  This paper presents a methodology for improving the reliability of power-gated designs by protecting the integrity of state retention registers through state monitoring and correction.  ...  ACKNOWLEDGMENT The authors would like to thank the EPSRC-UK for funding this work in part under grant number EP/E035965/1.  ... 
doi:10.1109/date.2010.5457233 dblp:conf/date/YangAFK10 fatcat:lrxb3e6tdne3rdcuk7h6o73swe

Hardware reliability of embedded systems: Are we there yet?

Bashir M. Al-Hashimi
2013 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)  
• Selective duplication • only insert RAZOR flip-flops in critical paths • Re-use existing circuitry • scan flip-flops in BISER • idle register files for redundancy Register files Low-Cost Hardware  ...  Flynn, and G. V. Merrett, "Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation," IEEE TCAS-I: Regular Papers, vol. 1, pp. 1-9, 2013.  ... 
doi:10.1109/patmos.2013.6662147 dblp:conf/patmos/Al-Hashimi13 fatcat:v6zdwlozkve2patkggprvg32ne

Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation

Sheng Yang, Saqib Khursheed, Bashir M. Al-Hashimi, David Flynn, Geoff V. Merrett
2013 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Through measurements from 82 test chips, each with a state retention block of 8192 flip-flops, implemented using 65-nm design library, we demonstrate that state integrity of a flip-flop is sensitive to  ...  Silicon results show that at characterized MRV, flip-flop state integrity is preserved, while achieving up to 17.6% reduction in retention voltage across 82-dies.  ...  ACKNOWLEDGEMENTS The authors would like to thank EuroPractice Mini-ASIC program for silicon fabrication and packaging, and Dr. Harry Oldham for his insightful comments.  ... 
doi:10.1109/tcsi.2013.2252640 fatcat:htlw64q2tbgn3g6xp3dp2jfwxm

On the design of two single event tolerant slave latches for scan delay testing

Yang Lu, Fabrizio Lombardi, Salvatore Pontarelli, Marco Ottavi
2012 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)  
The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature.  ...  The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32nm feature size as compared to the best design found  ...  Section II presents a review of soft error modeling and current designs for SEU tolerant flip-flops for scan delay testing.  ... 
doi:10.1109/dft.2012.6378202 dblp:conf/dft/LuLPO12 fatcat:carapcftv5f7dotx5dwb5qqcki

On-line fault detection for bus-based field programmable gate arrays

N.R. Shnidman, W.H. Mangione-Smith, M. Potkonjak
1998 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
His research interests include using dynamic circuits to implement configurable computing systems, low power processor and system design, multimedia and communications processing, and all techniques for  ...  From 1991 to 1995, he was employed by Motorola Inc., where he participated in the design of the Envoy Personal Digital Assistant.  ...  Parametric faults are related to design errors and include too low or too high output levels, insufficient fan-out driving capability, inadequate noise margin, and too short data retention interval.  ... 
doi:10.1109/92.736139 fatcat:zrqx27hg5bbzlcipaxiumy5ene

8. Conclusions

M. J. Yaffe, P. C. Bunch, L. Desponds, R. A. Jong, R. M. Nishikawa, M. J. Tapiovaara, K. C. Young
2009 Journal of the International Commission on Radiation Units and Measurements  
Acknowledgements The authors would like to express their gratitude to John Brzozowski for his useful comments and discussions on the topic of this paper.  ...  As a result, the scan data is stored in the first flip-flop and passed to the input of the second flip-flop.  ...  Sherlekar, "Issues in fault modelling and testing of micropipelines", First Asian Test Symposium, Hiroshima, Japan, Nov. 1992. [Pav94] N. C.  ... 
doi:10.1093/jicru/ndp024 pmid:24174602 fatcat:je4wonl2fbapjbnjbyl2xpasim

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test

Vasileios Tenentes, Saqib Khursheed, Daniele Rossi, Sheng Yang, Bashir M. Al-Hashimi
2015 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
To restore this test quality loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuckopen faults, we propose a design-for-testability (DFT) logic that accounts for a distributed  ...  To the best of our knowledge, this paper presents the first analysis of the PDN impact on test quality and offers a unified test solution for both ring and grid power gating styles.  ...  His research interests include fault modeling and design for reliability and test, focusing on low power and reliable digital design, robust design for soft error and aging resiliency, and high quality  ... 
doi:10.1109/tcad.2015.2446939 fatcat:gmny4v2ypjhktoevqa445bhdgi

Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions

Swarup Bhunia, Kaushik Roy
2007 2007 IEEE International Test Conference  
In this paper, we provide an overview of major low-power and variation-tolerant design techniques; discuss related test issues and focus on effectiveness of self-calibration/self-repair solutions to maintain  ...  Low-power and process-tolerant designs, however, impose new test challenges and may even have conflicting requirements for test -affecting delay fault coverage, I DDQ testability, parametric yield, and  ...  Extending the concept of data retention fault, a new fault model named low supply data retention fault is developed to describe flipping failures occurring due to application of low supply voltage in the  ... 
doi:10.1109/test.2007.4437659 dblp:conf/itc/BhuniaR07 fatcat:bdsfonjkkrhnxeigu3gog4y6de

Reconfigurable Hardened Latch and Flip-Flop for FPGAs

Hamzeh Ahangari, Ihsen Alouani, Ozcan Ozturk, Smail Niar
2017 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)  
In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flipflops (FFs) in reconfigurable  ...  Additionally, provided that special transistor sizing is applied (only necessary for some latch structures), JLatch and JFF take advantage of a novel selfcorrecting technique to correct any single fault  ...  In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel hardening solutions.  ... 
doi:10.1109/isvlsi.2017.82 dblp:conf/isvlsi/AhangariAON17 fatcat:gwnw64trx5ge3oobdb2r3jxj7i

High Quality Testing of Grid Style Power Gating

Vasileios Tenentes, Saqib Khursheed, Bashir M. Al-Hashimi, Shida Zhong, Sheng Yang
2014 2014 IEEE 23rd Asian Test Symposium  
To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the  ...  This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network  ...  The selected observation points number was in the range of [1 5 ] and the register files requirements (OP-REG + |C(f )|) are very low, in the range of [38 95] flip flops.  ... 
doi:10.1109/ats.2014.37 dblp:conf/ats/TenentesKAZY14 fatcat:uzfzxc2erraxzemkleu3ju6nj4

2021 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 29

2021 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
-that appeared in this periodical during 2021, and items from previous years that were commented upon or corrected in 2021.  ...  The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination.  ...  ., +, TVLSI May 2021 916-924 Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation.  ... 
doi:10.1109/tvlsi.2021.3136367 fatcat:fwqswbyzejgfhgbzywrvsf2qgi

Test Strategies for Low Power Devices

C. P. Ravikumar, M. Hirech, X. Wen
2008 2008 Design, Automation and Test in Europe  
This paper considers different aspects of testing low-power devices and some new techniques to address these problems.  ...  False failures may result due to the electrical and thermal stressing of the device in the test mode of operation, leading to yield loss.  ...  chip; (ii) Powerdown of selective power domains while ensuring proper isolation between shutdown and live parts, as well as ensuring proper retention of flip-flop states; (iii) Supply voltage scaling/switching  ... 
doi:10.1109/date.2008.4484765 dblp:conf/date/RavikumarHW08 fatcat:gyr3ki7a6ffohnuacq3vnhsyje

Test Strategies for Low-Power Devices

C. P. Ravikumar, M. Hirech, X. Wen
2008 Journal of Low Power Electronics  
This paper considers different aspects of testing low-power devices and some new techniques to address these problems.  ...  False failures may result due to the electrical and thermal stressing of the device in the test mode of operation, leading to yield loss.  ...  chip; (ii) Powerdown of selective power domains while ensuring proper isolation between shutdown and live parts, as well as ensuring proper retention of flip-flop states; (iii) Supply voltage scaling/switching  ... 
doi:10.1166/jolpe.2008.274 fatcat:6ubli656wvfdteygqpueg5bnqi

Test strategies for low power devices

C. P. Ravikumar, M. Hirech, X. Wen
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
This paper considers different aspects of testing low-power devices and some new techniques to address these problems.  ...  False failures may result due to the electrical and thermal stressing of the device in the test mode of operation, leading to yield loss.  ...  chip; (ii) Powerdown of selective power domains while ensuring proper isolation between shutdown and live parts, as well as ensuring proper retention of flip-flop states; (iii) Supply voltage scaling/switching  ... 
doi:10.1145/1403375.1403552 fatcat:weznrlc5xzbq5leqzg5bf7vi3e

A2: Analog Malicious Hardware

Kaiyuan Yang, Matthew Hicks, Qing Dong, Todd Austin, Dennis Sylvester
2016 2016 IEEE Symposium on Security and Privacy (SP)  
In the open spaces of an already placed and routed design, we construct a circuit that uses capacitors to siphon charge from nearby wires as they transition between digital values.  ...  When the capacitors fully charge, they deploy an attack that forces a victim flip-flop to a desired value.  ...  Any opinions, findings, conclusions, and recommendations expressed in this paper are solely those of the authors.  ... 
doi:10.1109/sp.2016.10 dblp:conf/sp/YangHDAS16 fatcat:rd6zdepquvhlnh7hqjcrjpn6oi
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