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A Built-In Self-Testing Method for Embedded Multiport Memory Arrays

V. Narayanan, S. Ghosh, W.-B. Jone, S.R. Das
2005 IEEE Transactions on Instrumentation and Measurement  
Chapter 5 discusses the application of the serial interfacing technique to detect coupling faults in multiport memories.  ...  Chapter 4 provides a detailed design of using the serial interfacing technique to test single-cell twoport faults in embedded memories.  ...  Note that we only need to consider 2PF2aa and 2PF2vv faults, since 2PF2av faults cannot occur at the same word.  ... 
doi:10.1109/tim.2005.855093 fatcat:knkdhn6dl5eevlb34chu6ao6fy

Introduction to Advanced Semiconductor Memories [chapter]

2009 Advanced Semiconductor Memories  
The demand for embedded memories is on the rise in current generation of ultra-large-scale integration (ULSI) and system-on-chip (SOC) level designs that require large amounts of SRAM, multiport RAM, DRAM  ...  Embedded SRAM is one of the most frequently used memory embedded in logic chips. Chapter 6 discusses embedded memory designs and applications.  ... 
doi:10.1109/9780470544136.ch1 fatcat:5agoaobfx5aqfmmsnmsj4a4mwy

Configurable Fault-Tolerance for a Configurable VLIW Processor [chapter]

Fakhar Anjam, Stephan Wong
2013 Lecture Notes in Computer Science  
Parity checking is utilized to detect errors in the instruction and data memories and the general register file (GR), while triple modular redundancy (TMR) approach is employed for all the synchronous  ...  The processor is parameterized and different parameters such as the issue-width, the number and types of different FUs, number of registers, memory buses, and latencies for the FUs can be chosen at design-time  ...  Parity checking is utilized to detect errors in the instruction and data memories, and the general register files (FPGA implementation).  ... 
doi:10.1007/978-3-642-36812-7_16 fatcat:aagbzgduyndk7brigcdaix6kxa

Recursive multiport schemes for implementing quantum algorithms with photonic integrated circuits

Gelo Noel M. Tabia
2016 Physical Review A  
We present recursive multiport schemes for implementing quantum Fourier transforms and the inversion step in Grover's algorithm on an integrated linear optics device.  ...  We find that high-fidelity performance is achievable with our multiport circuits for 2-qubit and 3-qubit quantum Fourier transforms, and for quantum search on four-item and eight-item databases.  ...  A photonic integrated circuit (PIC) is a multiport device consisting of an integrated system of optical elements embedded onto a single chip using a waveguide architecture [3, 4] .  ... 
doi:10.1103/physreva.93.012323 fatcat:yzacg7riynbptczrdwolb6rr6q

A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform

Joshua S. Monson, Mike Wirthlin, Brad Hutchings
2012 International Journal of Reconfigurable Computing  
Faults were injected via the Internal Configuration Access Port (ICAP).  ...  Using this density metric, we found that the most sensitive user module in the design was the PowerPC's direct connections to the DDR2 memory controller.  ...  The DDR2 is a multiported memory controller that has direct connections to the PowerPC through the IPLB and DPLB and also is connected through another port to the PLB.  ... 
doi:10.1155/2012/850487 fatcat:sbj7dfgqzvdglfj6qbfs2ys4xa

Fully parallel 30-MHz, 2.5-Mb CAM

F. Shafai, K.J. Schultz, G.F.R. Gibson, A.G. Bluschke, D.E. Somppi
1998 IEEE Journal of Solid-State Circuits  
Content addressable memories (CAM's) provide built-in hardware lookup capability with high speed and high flexibility in address allocation.  ...  One example of this approach is a bit-serial DRAM-based systolic associative memory [2] .  ...  INTRODUCTION I N content addressable memories (CAM's), data are accessed based on content rather than physical location.  ... 
doi:10.1109/4.726560 fatcat:gslrgjfqq5ae7g5ipb4z7nptdq

Linear embedding via Green's operators: A modeling technique for finite electromagnetic band-gap structures

A. M. van de Water, B. P. de Hon, M. C. van Beurden, A. G. Tijhuis, P. de Maagt
2005 Physical Review E  
Through an additional embedding step the equivalent sources describing the environment can be transferred to the boundary of the designated domain, rendering subsequent design steps very fast.  ...  In a cascade of embedding steps, separate reusable domains are combined to form larger domains.  ...  First, the current on C 1 generates a field that is propagated to C 2 , via the propagation operator P 21 .  ... 
doi:10.1103/physreve.72.056704 pmid:16383782 fatcat:xafglroecrgoliau5yisimk5la

The Online Temperature Measurement System for Substation Equipment Based on the Internet of Things (IOT)

Xiaoyan Ma, Hao Zou, Tingting Xu
2014 Modern Applied Science  
Finally, by the base station, it is transmit to the management center through the electric power communication network.  ...  In order to realize the real-time monitoring of temperature, wireless temperature sensor network is put in the temperature-measuring point in the substation, and then it is transit to the base station through  ...  The contingency and emergency of equipment temperature faults decide the fatality of temperature faults. Once the fault appears, there will be heavy loss.  ... 
doi:10.5539/mas.v8n3p217 fatcat:k5j7k5u5xncwpoeiaiaz5ijn34

Faster than real-time simulation

XioRui Liu, Juan Ospina, Ioannis Zografopoulos, Alonzo Russel, Charalambos Konstantinou
2021 Proceedings of the 9th Workshop on Modeling and Simulation of Cyber-Physical Energy Systems  
CCS CONCEPTS • General and reference → Surveys and overviews; • Computing methodologies → Parallel algorithms; • Computer systems organization → Embedded systems; • Hardware → Smart grid.  ...  outage faults, three-phase short circuit faults, etc.).  ...  Consequently, the solution can be reached through matrix-vector multiplication.  ... 
doi:10.1145/3470481.3472703 fatcat:z7xotikomrbltiqrdtoaf26lmq

Recent developments in high-level synthesis

Youn-Long Lin
1997 ACM Transactions on Design Automation of Electronic Systems  
NEW ARCHITECTURES Multiport Memory A multiport memory can support multiple read and/or write accesses simultaneously.  ...  Recently, HLS has been used in an embedded system design environment. A typical embedded system consists of off-the-shelf instruction set processors, memory, and ASICs.  ... 
doi:10.1145/250243.250245 fatcat:rtry5zc5y5gjbftnhetwxvvn7a

The "MIND" scalable PIM architecture [chapter]

Thomas Sterling, Maciej Brodowicz
2005 Advances in Parallel Computing  
MIND (Memory, Intelligence, and Network Device) is an advanced parallel computer architecture for high performance computing and scalable embedded processing.  ...  MIND is multicore with multiple memory/processor nodes on each chip and supports global shared memory across systems of MIND components.  ...  MEMORY MANAGER The memory manager provides the means of accessing the dynamic memory embedded in a PIM node.  ... 
doi:10.1016/s0927-5452(05)80010-3 fatcat:m7w6wqjxjrg3zowstdubiknvne

Towards silicon photonic neural networks for artificial intelligence

Bowen Bai, Haowen Shu, Xingjun Wang, Weiwen Zou
2020 Science China Information Sciences  
This paper walks through the basic concept of artificial neural networks and focuses on the key devices which construct the silicon photonic neuromorphic systems.  ...  [19] shows a new design for universal multiport interferometers using an alternative arrangement of programable MZIs, which has a much shorter optical depth and suffers less propagation loss compared  ...  When training the weight parameters in PNN, the output electrical signals are stored in the internal memory for conducting back-propagation algorithm using gradient descent method.  ... 
doi:10.1007/s11432-020-2872-3 fatcat:bftoqedp2rgkhesqdi4nzubjju

Fault Tolerant Implementations of Delay-Based Physically Unclonable Functions on FPGA

Durga Prasad Sahoo, Sikhar Patranabis, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty
2016 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)  
The proposed architectures can be used to detect run-time modifications in the PUF design due to fault injection.  ...  We validate the robustness of our proposed fault tolerant delay-based PUF designs on Xilinx Artix-7 FPGA platform.  ...  Then 'reset' is asserted to '0' and signal propagates through the loop to reach to a stable state.  ... 
doi:10.1109/fdtc.2016.10 dblp:conf/fdtc/SahooPMC16 fatcat:dr67xs6yx5f33luee32g5dywku

2018 Index IEEE Transactions on Power Delivery Vol. 33

2018 IEEE Transactions on Power Delivery  
., +, TPWRD Oct. 2018 2254-2264 A Novel Explicit Disturbance Model-Based Robust Damping of Interarea Oscillations Through MTDC Grids Embedded in AC Systems.  ...  Dattaray, P., +, TPWRD April 2018 728-740 A Novel Explicit Disturbance Model-Based Robust Damping of Interarea Oscillations Through MTDC Grids Embedded in AC Systems.  ... 
doi:10.1109/tpwrd.2018.2890521 fatcat:cdqlm4aaz5gwvisqhjcnkh66i4

KV-Cache: A Scalable High-Performance Web-Object Cache for Manycore

Daniel Waddington, Juan Colmenares, Jilong Kuang, Fengguang Song
2013 2013 IEEE/ACM 6th International Conference on Utility and Cloud Computing  
Caching of key-value pairs is performed solely in memory.  ...  KV-Cache's highly optimized architecture benefits from true "absolute" zero-copy by performing direct memory access (DMA) for each transmit and receive path, and eliminating any software memory copying  ...  page-fault handling. 5) Shared Memory Management -allocation of virtual memory space that is reserved for shared memory allocations.  ... 
doi:10.1109/ucc.2013.34 dblp:conf/ucc/WaddingtonCKS13 fatcat:inpww6lr4nhkbcgzrwmvmmospm
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