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A fully pipelined FPGA architecture for stochastic simulation of chemical systems

David B. Thomas, Hideharu Amano
2013 2013 23rd International Conference on Field programmable Logic and Applications  
Compared against existing chemical simulators on small to medium size chemical models, the new architecture is 30-100 times faster than a commercial software simulator running on an 8-core 3.4GHz Core  ...  i7, and 12-30 times faster than the best existing FPGA simulators.  ...  For models containing up to 62 reactions the new architecture is at least 70 times faster than an 8-core software simulator, and is 12 times faster than previous FPGA approaches.  ... 
doi:10.1109/fpl.2013.6645506 dblp:conf/fpl/ThomasA13 fatcat:qcuasvxg3jhwpb7kyax7nbpagy

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Javad Zarrin, Rui L. Aguiar, João Paulo Barraca
2017 Simulation modelling practice and theory  
Novel systems must be designed with great care and tools, such as manycore architecture simulators, must be adapted accordingly.  ...  Furthermore, the design of architecture simulators for manycore systems involve methods and techniques from various interdisciplinary research areas, which in turn brings more challenges in different aspects  ...  Furthermore, distributed memory simulators are more scalable than shared memory simulators and they can provide faster simulation by enabling cluster based simulation. • Parallel simulators are faster  ... 
doi:10.1016/j.simpat.2016.12.014 fatcat:j2acoyv235awfjkz6w7krvzh44

A Parallel Search Algorithm and Its Implementation for Digital k-Winners-Take-All Circuit

Myungchul Yoon
2015 JSTS Journal of Semiconductor Technology and Science  
The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations.  ...  Index Terms-k-winners-take-all, digital k-WTA circuit, parallel k-WTA, parallel search algorithm, scalable k-WTA architecture  ...  Through the simulations, the minimum clock periods (T c ) are obtained for the SLkWTA architecture and 2-level and 3-level MLkWTA architectures.  ... 
doi:10.5573/jsts.2015.15.4.477 fatcat:62rvqo3dvbcqhajd7wp3acs4xq

A proposed open cognitive architecture framework

Jeffrey S. Steinman, Craig N. Lammers, Maria E. Valinski
2009 Proceedings of the 2009 Winter Simulation Conference (WSC)  
This new cognitive architecture framework is combined with the Open Modeling and Simulation Architecture (OpenMSA) and the Open System Architecture for Modeling and Simulation (OSAMS) to form the foundation  ...  systems and modeling & simulation applications.  ...  paper would like to thank Dave Ferris, Chief Systems Engineer, Joint Program Executive Office for Chemical and Biological Defense (JPEO-CBD), who directs the Software Support Activity (SSA) Modeling, Simulation  ... 
doi:10.1109/wsc.2009.5429287 dblp:conf/wsc/SteinmanLV09 fatcat:usdn7xzfyvgf5asp2nqhinj7cm

Parallel fault-tolerant robot control

Deirdre L. Hamilton, John K. Bennett, Ian D. Walker, Jon D. Erickson
1992 Cooperative Intelligent Robotics in Space III  
Parallel control provides a faster response, which in turn allows a ner granularity o f c o n trol. Processor fault tolerance is also made possible by the existence of multiple processors.  ...  Most robot controllers today e m p l o y a single processor architecture.  ...  In this architecture, operations are pipelined through a three-stage switch n e t work.  ... 
doi:10.1117/12.131703 fatcat:dvk3omovgvbfjfq456olehwsty

PyBONDEM-GPU: A discrete element bonded particle Python research framework – Development and examples

Sven Dressler, Daniel N. Wilke, M.A. Aguirre, S. Luding, L.A. Pugnaloni, R. Soto
2021 EPJ Web of Conferences  
Graphics processing units (GPUs) are inherently designed for parallel computation, and recent advances in the architecture, compiler design and language development are allowing general-purpose computation  ...  Python is faster and easier to learn than classical compiled languages, making computational simulation development accessible to undergraduate and graduate engineers.  ...  Numba also supports execution on the parallel architecture of GPUs (13) (14) (15) .  ... 
doi:10.1051/epjconf/202124914009 fatcat:dxbl7c5nl5hztemm5fwbpwxaue

Appropriate Synchronization Time Allocation for Distributed Heterogeneous Parallel Computing Systems

2019 KSII Transactions on Internet and Information Systems  
NS3-cGEM5 simulator in this paper is formed by HLA-RTI federation integration of the two independent architecture and network simulators -NS3 and cGEM5.  ...  This paper presents a simulator used to test and allocate appropriate synchronization time for distributed and parallel heterogeneous systems.  ...  [8] have proposed Dist-GEM5 simulation tool to simulate the architectural structure and network behaviour of parallel and distributed heterogeneous computing systems.  ... 
doi:10.3837/tiis.2019.11.010 fatcat:bawjqgsjebgxpfr33cgqpsfe2a

High Speed 1-bit Bypass Adder Design for Low Precision Additions

Jong-Suk Lee, Dong Sam Ha
2007 2007 IEEE International Symposium on Circuits and Systems  
Simulation results show that the proposed adder is two times faster than existing adders for 8 bit additions.  ...  To support sub-word parallelism, the FleXilicon architecture adopts 8-bit processing units as the atomic operation.  ...  It is a coarse grained architecture, which provides massive parallel processing of loops.  ... 
doi:10.1109/iscas.2007.378200 dblp:conf/iscas/LeeH07 fatcat:ptvdf5bztnft7aficxvtj7tksu

Scalable instruction set simulator for thousand-core architectures running on GPGPUs

Shivani Raghav, Martino Ruggiero, David Atienza, Christian Pinto, Andrea Marongiu, Luca Benini
2010 2010 International Conference on High Performance Computing & Simulation  
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures.  ...  We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs  ...  Future architectures will expose a massive battery of parallel very-simple processors and on-chip memories connected through a network-on-chip, which speed is more than hundred times faster than the off-chip  ... 
doi:10.1109/hpcs.2010.5547092 dblp:conf/ieeehpcs/RaghavRAPMB10 fatcat:pymuffh3zvgbfp53r3lcruiabq

Hybrid CPU-GPU Distributed Framework for Large Scale Mobile Networks Simulation

Ben Romdhanne Bilel, Nikaein Navid, Mohamed Said Mosli Bouksiaa
2012 2012 IEEE/ACM 16th International Symposium on Distributed Simulation and Real Time Applications  
Cunetsim presents a proof of concept, demonstrating the feasibility of a fully GPU-based simulation rather than GPUoffloading or partial acceleration, through adequate architecture.  ...  are executed in parallel on GPU according to the master/worker model [13].  ...  The results also reveal that the existing simulators could be further improved through multi-core parallelism.  ... 
doi:10.1109/ds-rt.2012.15 dblp:conf/dsrt/BilelNB12 fatcat:7jixirvylnbuddbhwk3krmdls4

ARGoS: A modular, multi-engine simulator for heterogeneous swarm robotics

Carlo Pinciroli, Vito Trianni, Rehan O'Grady, Giovanni Pini, Arne Brutschy, Manuele Brambilla, Nithin Mathews, Eliseo Ferrante, Gianni Di Caro, Frederick Ducatelle, Timothy Stirling, Alvaro Gutierrez (+2 others)
2011 2011 IEEE/RSJ International Conference on Intelligent Robots and Systems  
Results show that ARGoS can simulate about 10,000 simple wheeled robots 40% faster than real-time.  ...  This feature enables entirely novel classes of optimizations to improve scalability and paves the way for a new approach to parallelism in robotics simulation.  ...  As a consequence, developing new modules is easy, despite the parallel nature of the ARGoS architecture.  ... 
doi:10.1109/iros.2011.6094829 dblp:conf/iros/PinciroliTOPBBMFCDSGGD11 fatcat:o6ziqzkjz5bbxbmrpgq6wxqot4

ARGoS: A modular, multi-engine simulator for heterogeneous swarm robotics

C. Pinciroli, V. Trianni, R. O'Grady, G. Pini, A. Brutschy, M. Brambilla, N. Mathews, E. Ferrante, G. Di Caro, F. Ducatelle, T. Stirling, A. Gutierrez (+2 others)
2011 2011 IEEE/RSJ International Conference on Intelligent Robots and Systems  
Results show that ARGoS can simulate about 10,000 simple wheeled robots 40% faster than real-time.  ...  This feature enables entirely novel classes of optimizations to improve scalability and paves the way for a new approach to parallelism in robotics simulation.  ...  As a consequence, developing new modules is easy, despite the parallel nature of the ARGoS architecture.  ... 
doi:10.1109/iros.2011.6048500 fatcat:emofvftje5el7me3kjpcgbj4jm

Faster than Real-Time Simulation: Methods, Tools, and Applications [article]

XiaoRui Liu, Juan Ospina, Ioannis Zografopoulos, Alonzo Russell, Charalambos Konstantinou
2021 arXiv   pre-print
Leveraging the real-time measurements of comprehensive system models, faster than real-time (FTRT) simulation allows the evaluation of system architectures at speeds faster than real-time.  ...  The acceleration of simulation times can be achieved by utilizing digital real-time simulators (RTS) and high-performance computing (HPC) architectures.  ...  For instance, an integrated AC/DC grid simulation is performed on a parallel FPGA-based architecture in [2] .  ... 
arXiv:2104.04149v1 fatcat:gvfr2j7kqzhevgnvq2poq6ee6e

Using ZPL to develop a parallel chaos router simulator

Wilkey Richardson, Mary L. Bailey, William H. Sanders
1996 Proceedings of the 28th conference on Winter simulation - WSC '96  
This paper reports on our experience in writing a parallel version of a chaos router simulator using the new datadriven parallel language ZPL.  ...  The (parallel) ZPL program is compared with the existing serial implementation on two very different architectures: a 16-processor Intel Paragon and a cluster of eight Alpha workstations.  ...  ) sequential simulator, and The portability of the parallel simulator and its ability to run on different architectures.  ... 
doi:10.1145/256562.256817 fatcat:oyajfmakzfca3dz5b62jmazjwe

XMT-GPU: A PRAM Architecture for Graphics Computation

Thomas M. DuBois, Bryant Lee, Yi Wang, Marc Olano, Uzi Vishkin
2008 2008 37th International Conference on Parallel Processing  
We test, through simulation and benchmarking, the potential performance impact of replacing these processors with a fully generalpurpose parallel processor, without the fixed-function graphics hardware  ...  The representative general-purpose processor we test against is XMT (for eXplicit Multi-Threading 1 ), a PRAM-like single-chip parallel architecture.  ...  Simulated Architecture We simulate an architecture consisting of XMT-based fragment processing, with all other portions of the GPU pipeline unchanged.  ... 
doi:10.1109/icpp.2008.35 dblp:conf/icpp/DuBoisLWOV08 fatcat:akjyvib4cngrnhwh6q523s3g6i
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